In advanced Back End of Line (BEOL) interconnect flows, the transition to copper metallization is essential to minimize the resistance-capacitance (RC) delay that limits device speed at sub-quarter-micron nodes and beyond P1.However, copper exhibits highly accelerated diffusion into silicon and low-κ dielectrics, which can form deep trap levels and cause severe device degradation P1.Consequently, this Ta-based liner deposition step is executed immediately after the MET3 dielectric trench etch an