What is the 40nm BSI CMOS Image Sensor process flow?

The 40nm BSI (Backside Illuminated) CMOS Image Sensor process flow is a specialized semiconductor manufacturing sequence for high-performance image sensors. Unlike traditional front-side illuminated (FSI) architecture, BSI places the photodiode beneath the metal interconnect layers and receives light from the wafer backside, dramatically improving quantum efficiency and low-light performance. This flow contains 417 process steps and is entirely free to access.

What is the difference between BSI and FSI image sensors?

In FSI architecture, incident light must pass through the metal interconnect layers to reach the photodiode — metal lines block and reflect some light, reducing quantum efficiency. BSI flips the wafer so light enters directly from the backside into the photodiode, bypassing the metal stack. This gives BSI sensors significantly higher sensitivity at the same pixel size, making them ideal for smartphone cameras and low-light applications.

What is the role of Deep Trench Isolation (DTI) in the 40nm CIS flow?

Deep Trench Isolation (DTI) creates physical and optical barriers between adjacent pixel photodiodes in BSI CIS. The trenches are filled with low-refractive-index material, preventing photo-generated carriers from diffusing into neighboring pixels (electrical crosstalk) and blocking oblique light from crossing pixel boundaries (optical crosstalk). This is critical for maintaining image quality as pixel pitch shrinks.

What is the role of Color Filter Array (CFA) and microlens in CIS?

The Color Filter Array sits above each pixel, arranging red, green, and blue filters in a Bayer pattern (RGGB) so each pixel captures only one color. The microlens array sits above the CFA, focusing incident light onto each pixel's active area to improve light collection efficiency. In BSI architecture, the shorter optical path and absence of metal obstruction simplify CFA and microlens alignment and increase the fill factor.

What are the key modules in the 40nm CIS process flow?

Key modules include: STI (Shallow Trench Isolation), Well formation, Gate, PD (Photodiode formation), F-DTI (Frontside Deep Trench Isolation), PMD/Contact, multi-level metal interconnect (MET0-MET6), DBI (Direct Bond Interconnect — wafer bonding), backside thinning (THIN), backside passivation (BKPAS), LS Grid (Light Shield Grid), CFA (Color Filter Array), microlens (UOCL), and Bondpad. The flow spans 42 modules and 417 process steps.

40nm BSI CMOS Image Sensor - 40nm 工艺流程

40nm BSI CMOS 图像传感器 (CIS) 工艺流程涵盖了背照式图像传感器从来料晶圆到彩色滤光片阵列和微透镜成型的完整制造过程。

与正照式 (FSI) 传感器不同，BSI 架构将光电二极管置于金属互连层下方，从减薄后的晶圆背面接收光线，从而实现更高的量子效率和更优的低光性能。

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关键工艺模块包括浅沟槽隔离 (STI)、光电二极管形成、正面深沟槽隔离 (F-DTI) 实现像素间光学和电学隔离、多层铜双大马士革互连 (MET0–MET6)、直接键合互连 (DBI) 实现晶圆与载片的键合、背面减薄与钝化、光屏蔽栅格抑制杂散光、Bayer 模式彩色滤光片阵列 (CFA) 以及微透镜制造。

本流程涵盖 417 个工艺步骤，横跨 42 个专业模块，为每个步骤提供基于学术论文、专利和权威教科书的详细原理分析和风险评估。工艺概述和模块地图公开可读。注册后可免费阅读 40nm 工艺的全部 417 个步骤。

40nm BSI CMOS 图像传感器 (CIS) 工艺流程涵盖了背照式图像传感器从来料晶圆到彩色滤光片阵列和微透镜成型的完整制造过程。

与正照式 (FSI) 传感器不同，BSI 架构将光电二极管置于金属互连层下方，从减薄后的晶圆背面接收光线，从而实现更高的量子效率和更优的低光性能。

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沿着截面变化理解每一步的作用，随时向 Ångström 提问。

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选择一个专题，深入理解关键工艺。

01像素感光与读出：光电二极管、扩散区和钉扎层3 站预览

看懂光电荷收集区、读出节点与表面钉扎区域如何依次建立。

开始专题导览

02背面集成：为什么先键合，再减薄与钝化3 站预览

看懂支撑、减薄与界面处理如何共同建立背面入光结构。

开始专题导览

03像素光学：分色、平坦化与聚光3 站预览

看懂分色结构、平坦基底与微透镜如何共同引导入射光。

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步骤正文按当前阅读权限开放。

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