Complete 40nm→7nm flows, rendered step-by-step in 2.5D cross-sections and grounded in papers, patents & textbooks — with an AI you can ask. Every claim cited.
Process flow visualization

4 technology nodes · 40nm→7nm · 2.5D cross-sections
Sample answer
Why must the high-k layer in HKMG be deposited by ALD?
In HKMG integration, high-k dielectrics such as HfO₂ must be deposited by atomic layer deposition (ALD) rather than CVD/PVD: ALD's self-limiting surface reactions give sub-nanometer thickness control and excellent conformality , critical for EOT scaling and gate-leakage control . Layer-by-layer growth of the interfacial layer and high-k also suppresses oxygen-vacancy defects, reducing threshold-voltage shift .
Atomic Layer Deposition of High-κ Dielectrics
(2018)
EOT Scaling and Gate Leakage in HKMG Stacks
2016
General AI is a good tool, but semiconductor processes demand a specialized engine
Extensive papers + patents + textbooks — every answer tagged with [T1][P2][A3] source IDs, traceable to original text
General AI: general internet corpus, frequently fabricates non-existent references
Automatically infers process type and functional role, with deep mechanism analysis grounded in paper data and patented solutions
General AI: stays at textbook overview level, unaware of relationships between process steps
Step-by-step navigation of 1,700+-step flows (40nm CIS / 28nm / 14nm / 7nm), plus a 2D process cross-section for each step to watch the material stack take shape (live for 28nm and 14nm, more nodes rolling out)
General AI: text-only output, no process flow visualization
Two parallel offerings — mix freely: process-flow nodes (one-time, lifetime) + AI deep Q&A (subscription, free tier included)
One-time purchase, lifetime access
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Smart reasoning + deep knowledge retrieval
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Common questions about the SemiFlows platform
SemiFlows is an AI-powered semiconductor process knowledge platform that provides complete, step-by-step process flows from 40nm to 7nm, covering both logic chips and CMOS image sensors. It integrates extensive research papers, patents, and authoritative textbooks to deliver in-depth rationale analysis with citation tracing for each process step. The 40nm BSI CIS flow is entirely free.
SemiFlows currently covers four process flows: 40nm BSI CMOS Image Sensor (417 steps, free), 28nm Planar (266 steps), 14nm FinFET (362 steps), and 7nm FinFET (716 steps). Together, these flows provide over 1,700 detailed process steps spanning both logic chip and image sensor fabrication.
Unlike general AI assistants, SemiFlows is purpose-built for semiconductor process engineering. Every answer is grounded in curated academic papers, patents, and textbooks — not general internet knowledge. The platform provides citation-backed explanations with traceable references, structured process flows, and domain-specific context that general AI tools cannot match.
SemiFlows provides physics and chemistry principles behind each process step, mechanism explanations (why a process works), integration rationale (why steps are ordered a certain way), and risk analysis. All content focuses on fundamental principles — not specific manufacturing recipes, equipment parameters, or vendor details.
Yes. SemiFlows supports both English and Chinese (中文). Users can switch languages at any time using the language toggle. The AI chat assistant also responds in the user's selected language.