Frequently Asked Questions

SemiFlows is an AI-powered semiconductor process knowledge platform that provides complete, step-by-step process flows from 40nm to 7nm, covering both logic chips and CMOS image sensors. It integrates extensive research papers, patents, and authoritative textbooks to deliver in-depth rationale analysis with citation tracing for each process step. The 40nm BSI CIS flow is entirely free.

SemiFlows currently covers four process flows: 40nm BSI CMOS Image Sensor (417 steps, free), 28nm Planar (341 steps), 14nm FinFET (353 steps), and 7nm FinFET (716 steps). Together, these flows provide over 1,800 detailed process steps spanning both logic chip and image sensor fabrication.

Unlike general AI assistants, SemiFlows is purpose-built for semiconductor process engineering. Every answer is grounded in curated academic papers, patents, and textbooks — not general internet knowledge. The platform provides citation-backed explanations with traceable references, structured process flows, and domain-specific context that general AI tools cannot match.

SemiFlows provides physics and chemistry principles behind each process step, mechanism explanations (why a process works), integration rationale (why steps are ordered a certain way), and risk analysis. All content focuses on fundamental principles — not specific manufacturing recipes, equipment parameters, or vendor details.

Yes. SemiFlows supports both English and Chinese (中文). Users can switch languages at any time using the language toggle. The AI chat assistant also responds in the user's selected language.

The 40nm BSI (Backside Illuminated) CMOS Image Sensor process flow is a specialized semiconductor manufacturing sequence for high-performance image sensors. Unlike traditional front-side illuminated (FSI) architecture, BSI places the photodiode beneath the metal interconnect layers and receives light from the wafer backside, dramatically improving quantum efficiency and low-light performance. This flow contains 417 process steps and is entirely free to access.

In FSI architecture, incident light must pass through the metal interconnect layers to reach the photodiode — metal lines block and reflect some light, reducing quantum efficiency. BSI flips the wafer so light enters directly from the backside into the photodiode, bypassing the metal stack. This gives BSI sensors significantly higher sensitivity at the same pixel size, making them ideal for smartphone cameras and low-light applications.

Deep Trench Isolation (DTI) creates physical and optical barriers between adjacent pixel photodiodes in BSI CIS. The trenches are filled with low-refractive-index material, preventing photo-generated carriers from diffusing into neighboring pixels (electrical crosstalk) and blocking oblique light from crossing pixel boundaries (optical crosstalk). This is critical for maintaining image quality as pixel pitch shrinks.

The Color Filter Array sits above each pixel, arranging red, green, and blue filters in a Bayer pattern (RGGB) so each pixel captures only one color. The microlens array sits above the CFA, focusing incident light onto each pixel's active area to improve light collection efficiency. In BSI architecture, the shorter optical path and absence of metal obstruction simplify CFA and microlens alignment and increase the fill factor.

Key modules include: STI (Shallow Trench Isolation), Well formation, Gate, PD (Photodiode formation), F-DTI (Frontside Deep Trench Isolation), PMD/Contact, multi-level metal interconnect (MET0-MET6), DBI (Direct Bond Interconnect — wafer bonding), backside thinning (THIN), backside passivation (BKPAS), LS Grid (Light Shield Grid), CFA (Color Filter Array), microlens (UOCL), and Bondpad. The flow spans 42 modules and 417 process steps.

The 28nm Planar process flow is a semiconductor manufacturing sequence that uses a Gate-Last HKMG (High-K Metal Gate) replacement gate integration scheme. A dummy polysilicon gate is formed first, then replaced with high-k dielectric and metal gate materials after source/drain activation, enabling better threshold voltage control and lower gate leakage compared to gate-first approaches.

The 28nm Planar process flow on SemiFlows contains 341 detailed process steps, covering the complete front-end-of-line (FEOL) and back-end-of-line (BEOL) integration from STI formation through metal interconnects.

Key modules include STI (Shallow Trench Isolation), Gate formation with high-k/metal gate replacement, Spacer engineering, Source/Drain epitaxy and implant, Contact formation, and multi-level metal interconnect (M1 and above). Each module involves multiple deposition, lithography, etch, and CMP steps.

Gate-last (replacement metal gate) is preferred at 28nm because it avoids exposing the high-k dielectric and metal gate to high-temperature source/drain activation anneals. This preserves the work function metal properties and enables independent NMOS/PFET threshold voltage tuning, which is critical for low-power and high-performance applications.

The 14nm FinFET process flow is an advanced semiconductor manufacturing sequence that uses three-dimensional fin-shaped transistor structures instead of planar transistors. The fins provide better electrostatic control of the channel, significantly reducing short-channel effects and leakage current while enabling continued scaling beyond the limits of planar technology.

The primary difference is the transistor architecture: 14nm uses 3D fin structures where the gate wraps around the channel on three sides, while 28nm uses traditional planar (flat) transistors. This tri-gate structure provides superior electrostatic control, enabling ~50% power reduction or ~20% performance improvement at the same power. The process flow also introduces new modules like fin patterning (SADP/SAQP), fin recess, and epitaxial source/drain wrapping around fins.

The 14nm FinFET process flow on SemiFlows contains 353 detailed process steps, spanning fin formation, gate patterning, source/drain engineering, contact metallization, and back-end-of-line interconnects.

SADP (Self-Aligned Double Patterning) is a lithography technique used in 14nm FinFET manufacturing to create fin patterns at pitches below the resolution limit of single-exposure lithography. It involves depositing a conformal spacer film on mandrel structures, then removing the mandrels to leave spacer pairs that define the fin locations at half the mandrel pitch.

The 7nm FinFET process flow represents one of the most advanced semiconductor manufacturing nodes using immersion lithography (without EUV). It combines aggressive fin pitch scaling, self-aligned quadruple patterning (SAQP), advanced strain engineering, and cobalt-based contacts to achieve significant density and performance improvements over 14nm and 10nm nodes.

The 7nm FinFET process flow on SemiFlows contains 716 detailed process steps, making it the most comprehensive flow on the platform. It covers the complete integration from wafer preparation through 12+ metal layers. Note: metal layers M4-M8 share an identical process sequence and are represented as a single template layer.

The 7nm node primarily uses Self-Aligned Quadruple Patterning (SAQP) for critical layers like fins, combined with Litho-Etch-Litho-Etch (LELE) for other tight-pitch layers. SAQP extends immersion lithography to achieve sub-40nm pitches without requiring EUV lithography, though at the cost of increased process complexity and more patterning steps.

Key innovations at 7nm include: tighter fin pitch via SAQP (vs SADP at 14nm), cobalt contacts and local interconnects replacing tungsten for lower resistance, more aggressive gate length scaling, advanced epitaxial source/drain profiles, and 12+ metal interconnect layers with copper dual-damascene and advanced barrier metals.

Cobalt plays a critical role at 7nm as a replacement for tungsten in middle-of-line contacts (MOL). As contact dimensions shrink, tungsten's high resistivity barrier liner consumes too much of the contact volume. Cobalt offers lower bulk resistivity and thinner barriers, significantly reducing contact resistance. It is used in trench contacts (CB/CA) and via-to-contact connections (VC).

SemiFlows uses a two-tier pricing model: (1) One-time purchase of process flow content per technology node (28nm $49, 14nm $149, 7nm $349), or the All-Node Bundle at $449 (18% discount), with lifetime access; (2) Optional AI Pro subscription ($39/mo or $349/yr) for deep AI conversations and advanced reasoning engine. Free users can try basic AI Q&A and flow previews.

Yes, we offer a refund policy. Please refer to our Refund Policy page for specific terms. All payments are processed by Paddle.com as the Merchant of Record, and refund requests are handled through Paddle.

You can manage your subscription in account settings, including upgrades, downgrades, or cancellation. Subscriptions are handled through Paddle, where you can view billing history and manage payment methods in Paddle's customer portal. After cancellation, Pro features remain available until the end of the current billing period.

SemiFlows accepts various payment methods through Paddle, including credit cards (Visa, Mastercard, American Express), PayPal, and local payment methods in select regions. Paddle automatically handles tax calculation and invoicing.

SemiFlows uses Retrieval-Augmented Generation (RAG) technology. When you ask a question, the system first retrieves the most relevant paper, patent, and textbook passages from the knowledge base, then provides this context to the AI model to generate citation-backed answers. This ensures every response is grounded in real academic sources rather than the model's general training data.

Citation markers indicate the source of information in answers: [T] for Textbooks, [P] for Papers, and [A] for pAtents. The number corresponds to the specific retrieved document. For example, [P2] means the information comes from the 2nd retrieved paper. This annotation lets you trace every piece of information back to its original source.

The Free plan offers limited daily AI Q&A with quick answer mode and basic citations. The Pro plan ($39/mo) provides generous daily conversations, an advanced reasoning engine with deep knowledge retrieval, full citation tracing across all three source types, and process context analysis.

Yes. The AI chat assistant supports both Chinese and English. The system automatically responds in the language you've selected in the interface. Regardless of which language you use, the underlying knowledge retrieval covers the full corpus of papers, patents, and textbooks.

SemiFlows covers complete process flows from 40nm to 7nm, including 40nm BSI CMOS Image Sensor (free), 28nm Planar, 14nm FinFET, and 7nm FinFET — totaling over 1,800 process steps. Content focuses on physics and chemistry principles, mechanism explanations, integration rationale, and risk analysis — without specific manufacturing parameters, equipment models, or vendor information.

The knowledge base is continuously expanded with newly published research papers and patents. Process flow content is released after multi-layer quality validation, with rationale analysis and risk assessment for each step grounded in current academic literature. The platform is regularly updated to incorporate new research findings and technical insights.

SemiFlows knowledge comes from three authoritative source types: (1) Research papers covering major semiconductor journals and top conferences; (2) Public process patent literature; (3) Classic textbooks in semiconductor manufacturing. All sources undergo pre-evaluation and quality screening to ensure high relevance to semiconductor processes.

After signing up with email or Google for a free account, you can immediately preview the first few steps of all process flows and try basic AI Q&A. Purchasing any technology node unlocks all step content for that node. For AI deep analysis features (advanced reasoning engine + deep knowledge retrieval), subscribe to the Pro plan.

You can reach our support team at support@semiflows.com. We typically respond within 1-2 business days. Whether it's a technical issue, account question, or product feedback, we're happy to help.

SemiFlows is a web application that supports all modern browsers, including the latest versions of Chrome, Firefox, Safari, and Edge. The platform uses responsive design and fully supports desktop, tablet, and mobile devices, with a complete experience on all screen sizes.

Click the 'Forgot password?' link on the login page and enter your email. The system will send a password reset link. Click the link in the email to set a new password. If you don't receive it, check your spam folder. You can also sign in with Google — no password needed.

You can find the 'Delete Account' option at the bottom of the Account Settings page. Please note: this action is irreversible — all account data including conversation history and purchase records will be permanently deleted. If you have an active subscription, please cancel it before deleting your account.

Yes. SemiFlows takes data security seriously: all communications are encrypted via HTTPS; passwords are securely hashed; payment information is handled by Paddle (a PCI DSS compliant payment processor) — SemiFlows never stores payment card details. Your AI conversation content is only used to provide the service and is not used to train AI models. See our Privacy Policy page for details.