The P+ VSS and Periphery P-Well Contact IIP - Photo step is a critical photolithography operation designed to define the spatial windows for a subsequent high-dose p-type ion implantation T1.In the context of a 40nm BSI CMOS Image Sensor, the periphery logic and readout circuitry require stable electrical connections to the P-Well (body) and the VSS (ground) plane (Engineering Practice).Unlike the earlier "Periphery P-Well IIP - Photo" step which defines the deep, lightly doped well region, this