The VSS and Periphery P-Well Contact Ion Implantation (IIP) step immediately follows photolithographic patterning to selectively dope the ground connections in the pixel array and the body contacts in the periphery logic P4.Its primary objective is to create a heavily doped P+ region that enables the formation of a low-resistance ohmic contact between the silicon substrate and the subsequent metallization layers T2.This step is functionally distinct from the earlier Periphery P-Well IIP (step #5