40nm BSI CMOS Image SensorPreview

ed to form the VSS and Periphery P-Well contacts, and crucially prepares the wafer for the subsequent high-temperature Dopants Activation anneal [A6]. During the upstream implantation, the photoresist mask absorbs a massive flux of high-energy dopant ions, which physically damages the resist polymer chains and chemically depletes hydrogen to leave a highly cross-linked, carbonized surface crust [A4]. As noted in analogous implantation masking processes, the mask layer must be completely removed by stripping or etching after the ion implantation operations are completed to ensure device integrity [A5]. If this hardened resist and the post-implant residues are not thoroughly eliminated, the subsequent high-temperature dopant activation anneal will drive residual carbon and metallic contaminants deep into the silicon lattice [P1]. These incorporated impurities would form deep-level recombination centers that distort the band structure and severely degrade the efficient tunneling contact transport required for low-resistance metal-semiconductor junctions [T1]. Unlike earlier baseline photoresist strips in the flow, this particular step must aggressively dismantle an implant-hardened crust without simultaneously consuming the underlying highly doped silicon or recessing adjacent isolation oxides [A4]. The physical mechanism of this step relies on a synergistic two-stage process: reactive plasma ashing followed by wet chemical stripping [A2]. The plasma ashing phase introduces reactive oxygen and reducing gas radicals to physically bombard and chemically oxidize the carbonized resist crust, converting the dense organic polymers into volatile compounds such as carbon dioxide and water vapor [A2]. Because the heavily cross-linked outer layer firmly resists pure chemical attack, the plasma process is strictly required to breach this shell and expose the underlying unaltered photoresist, a mechanism similar to the controlled ashing processes used to expose underlying pre-gate structures in thin-film transistor manufacturing [A4]. Following the dry ash, a wet stripping composition is applied to dissolve trace organic residues, remove residual inorganic implantation byproducts, and strip the transient oxide formed during the plasma step [A2]. Modern wet stripping compositions utilize carefully selected oxidizing agents to digest these stubborn residues while employing corrosion inhibitors and chelators to protect the newly exposed semiconductor surfaces, functioning much like the selective wet cleans formulated for complex post-plasma etch residues [A2]. Material and chemistry selection for this step is heavily dictated by the need to balance residue removal against substrate preservation [A2]. The ashing plasma chemistry relies on a tailored mixture of oxygen and reducing gases to mitigate the aggressive oxidation of the exposed shallow contact silicon [A2]. Excessive silicon oxidation during the ashing phase would physically consume the most heavily doped portion of the surface layer, pushing the eventual metal-semiconductor interface deeper into the substrate and unfavorably altering the effective barrier height and tunneling probability described in classical contact transport models [T1]. For the wet clean phase, solutions containing specialized ammonium-based oxidizers or weak organic acids are preferred over aggressive hydrofluoric acid-based cleans, as they selectively dissolve implantation-induced metallic contaminants without excessively etching the field oxide [A2]. The interaction between plasma power, gas flow ratios, and wet clean reactivity must be strictly co-optimized; higher plasma power effectively shatters the implant crust but exponentially increases the risk of substrate lattice damage and oxidation, while milder wet cleans protect isolation dielectrics but require prolonged process times to achieve full residue dissolution [A2]. In the context of a 40nm BSI CMOS Image Sensor, the physical scaling of the contact windows fundamentally constrains the strip process window (Engineering Practice). The ultra-shallow junction depths of the nanoscale P+ contacts leave virtually zero margin for silicon loss during the oxidation and stripping phases [A6]. Furthermore, the geometric confinement of the nanoscale contact trenches makes it exceedingly difficult for wet chemicals to penetrate and flush out residues due to dominant capillary forces at this scale (Engineering Practice). Consequently, the stripping compositions must possess precisely tuned viscosity and wetting properties to ensure complete residue removal from the bottom of high-aspect-ratio features, as similar residue-removal challenges and dielectric compatibility issues are known to scale directly with shrinking device dimensions [A2].