This step defines the geometric pattern for the topmost metal interconnect layer (Metal 8), specifically functioning as the Direct Bond Interconnect (DBI) pads in a 3D-stacked BSI CMOS Image Sensor A1.Following the deposition of the inter-level dielectrics (ILD 6-5 and ILD 6-6/WBL) and pre-litho cleaning, photoresist is exposed and developed to create the trench template for subsequent dielectric etching A2.Unlike intermediate BEOL routing layers such as Metal 0 or Metal 1, or front-end steps li