Photoresist exposure and development create the trench template for subsequent dielectric etching .
In depth
This step defines the geometric pattern for the topmost metal interconnect layer (Metal 8), specifically functioning as the Direct Bond Interconnect (DBI) pads in a 3D-stacked BSI CMOS Image Sensor
. Following the deposition of the inter-level dielectrics (ILD 6-5 and ILD 6-6/WBL) and pre-litho cleaning, photoresist is exposed and developed to create the trench template for subsequent dielectric etching . Unlike intermediate BEOL routing layers such as Metal 0 or Metal 1, or front-end steps like STI and Deep Trench isolation, the Metal 8 DBI pad lithography is strictly governed by the stringent alignment requirements of subsequent die-to-die or wafer-to-wafer hybrid bonding . The exact positioning, pitch, and critical dimension (CD) defined here directly dictate the overlay margin when mating this CIS die to a corresponding logic or memory die . The lithographic process operates on the principle of optical diffraction limits, where the minimum resolvable feature size is governed by the Rayleigh equation . Because hybrid bonding often targets sub-micrometre-scale or even sub-micrometre-scale pitches, maximizing numerical aperture and applying advanced optical proximity correction (OPC) is essential to ensure sharp trench profiles and prevent systematic variations caused by adjacent pattern interference [P1, T3]. The photoresist undergoes a photochemical reaction upon exposure, changing its solubility in the developer to define the trench areas (Engineering Practice). The precision of this pattern transfer is critical because the final copper pads will be formed inside these trenches via a damascene process, which includes Cu deposition followed by chemical-mechanical polishing (CMP) . The geometry defined at this step, such as designing asymmetric pad sizes for the top and bottom wafers, is a structural mechanism used to increase tolerance for wafer alignment errors during the subsequent bonding phase . The photoresist and anti-reflective coating materials are selected to minimize reflection from the underlying ILD stack, ensuring tight CD control and minimizing line-edge roughness, which is a form of random device variation . Process parameters such as exposure dose and focus are tightly coupled; dose controls the trench width, while focus determines the sidewall angle of the resist profile (Engineering Practice). Maintaining an exact pad size is critical for the hybrid bonding thermodynamic mechanisms: during post-bond annealing at 150–400 °C, the Cu atoms must expand and diffuse across the nanoscale interface gap [P1, P2]. If the lithographically defined pad area is too small, insufficient Cu volume may lead to inadequate thermal expansion and failure to close the gap . Conversely, excessively large pads could exacerbate Cu dishing during the later CMP step, rendering the gap too large for atomic interdiffusion . In a 40nm BSI CMOS Image Sensor architecture, the pixel array density demands exceptionally high interconnect density to the underlying signal processing logic, achieving interconnect densities greater than 10^6 cm^-2 . Scaling the DBI pads to support this density necessitates ultra-fine pitch lithography that pushes the limits of standard backend alignment capabilities . Furthermore, defining precisely controlled pad geometries helps mitigate Cu diffusion and migration reliability concerns as the dimensions approach those of the global back-end of line metal layers .
Risks & Challenges
[High] Overlay / Alignment Error: Misalignment during this photo step shifts the entire DBI pad array relative to the mating wafer's pads, which reduces the effective contact area for Cu-Cu atomic interdiffusion and leads to high resistance or open circuits during hybrid bonding [P1, P3].
[Medium] Critical Dimension (CD) Variation: Focus or dose drifts cause the defined pad trenches to be too narrow, providing insufficient copper volume for adequate thermal expansion during the low-temperature batch anneal, thereby preventing the closure of the interface gap .
[Medium] Poor Sidewall Profile / Line Edge Roughness: Granularity in the photoresist causes wave-like edges on the pad trenches, transferring roughness into the final Cu pad which can disrupt the delicate interfacial free energy minimization required for spontaneous dielectric bonding [P2, T3].
[Low] Resist Scumming: Unremoved photoresist residue at the bottom of the trench impedes the subsequent dielectric etch, creating varying trench depths that disrupt the volumetric balance required for the final CMP to achieve the precisely targeted 5–nanoscale Cu protrusion or recess .