equipment bias voltage is carefully tuned to provide enough directional energy for anisotropy without causing catastrophic physical sputtering of the trench bottom or degrading the remaining bonding dielectric's surface properties .
In 40nm BSI CMOS image sensors, 3D heterogeneous integration rel
ies heavily on Direct Bond Interconnect (DBI) technology to join the sensor array with the logic die . The ILD 6-5 Etch step is a critical BEOL dry etching process designed to define the dielectric trenches for the subsequent Metal 8 DBI pads . Positioned immediately after the Wafer Bonding Layer (WBL) etch, this step selectively transfers the photolithographically defined trench pattern deep into the bulk ILD 6 dielectric stack . This precise material removal prepares the physical cavity that will later be filled with copper and subjected to chemical-mechanical polishing (CMP) to achieve the sub-nanometer surface planarity required for reliable Cu-to-Cu and dielectric-to-dielectric hybrid bonding . Furthermore, it serves as the foundational structure for the subsequent Via 7 patterning, establishing the interconnect hierarchy essential for dual damascene or self-aligned interconnect flows . The etching of the silicon-based dielectric is driven by a fluorinated plasma chemistry, utilizing the synergistic effects of chemical reaction and physical ion bombardment . In the plasma chamber, fluorocarbon gases (such as CF4 or CHF3) dissociate to generate highly reactive fluorine atoms and CFx radicals . The fluorine atoms chemically react with the silicon-oxygen-carbon-nitrogen network of the ILD to form volatile byproducts like SiF4, COx, and NOx, which are rapidly pumped away from the system . Concurrently, anisotropic physical bombardment by energetic ions accelerates the localized breaking of surface bonds and promotes the desorption of these reaction products at the trench bottom, ensuring a highly vertical etch profile . The balance between polymerizing CFx radicals—which form a protective fluorocarbon passivation layer on the trench sidewalls—and the aggressive ion bombardment at the trench bottom dictates the final critical dimension (CD) and sidewall angle . The selection of specific fluorocarbon ratios and ion energy parameters is fundamentally dictated by the need to maintain strict etch selectivity between the ILD material and the overlying mask or underlying etch-stop layers . Introducing oxygen into the plasma can tune the relative etch rate by modulating the surface polymer thickness, which is critical when etching complex composite dielectric stacks . Furthermore, because the ultimate goal is hybrid wafer-to-wafer bonding, the structural integrity of the dielectric must be perfectly preserved . Over-etching or uncontrolled ion energy can induce subsurface damage or micro-trenching, similar to the substrate damage mechanisms observed during plasma over-etching in metal plug processes . Therefore, equipment bias voltage is carefully tuned to provide enough directional energy for anisotropy without causing catastrophic physical sputtering of the trench bottom or degrading the remaining bonding dielectric's surface properties . At the 40nm node for BSI sensors, the scaling of the DBI pad pitch to sub-micrometre-scale dimensions necessitates extremely tight control over the etch profile and interconnect parasitics . As device dimensions shrink, subthreshold leakage and RC delays become prominent constraints on overall sensor system performance . To mitigate these issues, the ILD stack often incorporates specialized SiCN or low-k materials that present unique etching challenges compared to traditional SiO2 . The ILD 6-5 Etch must precisely navigate these multi-layer dielectric transitions without introducing via-trench chamfering or structural bowing, which could otherwise lead to severe via-trench leakage or hybrid bonding failure at these aggressive pitches .
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