The physical ion bombardment provides directionality to achieve highly vertical trench sidewalls, analogous to the anisotropic etching principles leveraged for vertical interconnects in .
The ILD 6-6 (Wafer Bonding Layer, WBL) Etch is a critical front-end step for establishing the structural foun
dation of Direct Bond Interconnects (DBI) in heterogeneous integration . Following the deposition of the WBL and subsequent trench lithography, this dry etching process transfers the Metal 8 DBI pad patterns into the topmost dielectric layer . This defines the dielectric field regions that will eventually surround the top-level Cu pads . Creating precise trenches is imperative because hybrid bonding requires joining slightly recessed or geometrically controlled Cu interconnects patterned within this dielectric field . The accurate depth and profile control during this etch set the stage for the subsequent ILD 6-5 etch and eventual metallization and chemical-mechanical polishing (CMP) steps that dictate the final pre-bond surface topography . The etching of the WBL relies on an anisotropic plasma etch process driven by reactive ion etching principles (Engineering Practice). In the plasma environment, fluorocarbon-based precursor gases dissociate into reactive radicals and energetic ions, establishing a chemical and physical etching synergy (Engineering Practice). The physical ion bombardment provides directionality to achieve highly vertical trench sidewalls, analogous to the anisotropic etching principles leveraged for vertical interconnects in . Careful control of the etch profile is required to avoid forming sharp corners or irregular geometries, which can cause localized electric field concentration and degrade device reliability, as governed by the geometric field effects described in . Furthermore, maintaining the structural integrity of the unetched dielectric surface during plasma processing is vital . This is because the final WBL surface must remain pristine to participate in dielectric-to-dielectric van der Waals and covalent bonding during the initial room-temperature phase of the two-step DBI process . The selection of a highly anisotropic dry etch for the WBL is dictated by the requirement for ultra-fine sub-micron pitch control . Parameter tuning—such as adjusting the ratio of polymerizing to etching gases in the plasma—directly influences the etch selectivity and the final sidewall angle . High selectivity to an underlying etch stop layer is often utilized to precisely terminate the etch depth, ensuring uniform trench volumes across the wafer . This uniformity is crucial because deviations in trench depth propagate through the subsequent Cu fill and CMP processes . These deviations directly alter the critical Cu recess depth that fundamentally determines whether the Cu-Cu interconnects will successfully close during post-bond thermal expansion and atomic diffusion . If an alternative dielectric like SiCN is used to facilitate low-temperature bonding, the etch chemistry must be co-optimized to handle the specific surface reactivity of the material . For a nanoscale Backside Illuminated (BSI) CMOS Image Sensor, the pixel density demands an extremely fine interconnect pitch to route signals effectively between the sensor array and the underlying logic die . As the DBI pad pitch scales down to accommodate high-density partitioning, the etch process must maintain strict critical dimension (CD) uniformity . It must avoid inducing micro-trenching or dielectric damage that could compromise the ultra-low surface roughness required for spontaneous dielectric bonding . Additionally, the process must ensure that the etched trenches align perfectly with the subsequent via structures to mitigate Cu diffusion or migration reliability concerns as interconnect dimensions shrink .
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