Ashing & Strip/Clean - 40nm

Consequently, modern stripping compositions are formulated with buffering agents and specific corrosion inhibitors that modulate the local pH and selectively passivate vulnerable surfaces during the residue oxidation process .

In the process flow for a 40nm BSI CMOS Image Sensor, this specific As

hing & Strip/Clean step immediately follows the ILD 6-5 Etch, which physically defines the trench for the top-level Metal 8 Direct Bond Interconnect (DBI) pad . The primary function of this step is to completely remove the bulk photoresist mask and the stubborn fluorocarbon-based polymeric residues generated during the preceding Reactive Ion Etching (RIE) process . Unlike upstream routine clean steps, this operation is uniquely critical because it prepares the trench topography for the subsequent VIA 7 photolithography step within a trench-first or partial-trench dual damascene integration scheme . Any residual polymers or non-uniform topography left at this stage will degrade the surface planarity, leading to thickness variations in the subsequent bottom resist coating and precipitating pattern collapse or critical dimension (CD) variations during via patterning . Furthermore, because this trench will ultimately house the Cu pad for dielectric-to-dielectric and metal-to-metal hybrid bonding, preserving the structural and chemical integrity of the surrounding ILD is paramount for eventual sub-micron pitch die-to-die hybridization [P1, A1]. The physical mechanism of this step relies on a two-part sequence: dry plasma ashing followed by wet chemical stripping . During the dry phase, an oxygen-based plasma chemically oxidizes the organic photoresist into volatile byproducts such as carbon monoxide, carbon dioxide, and water vapor, which are subsequently evacuated from the process chamber . However, post-plasma etch residues typically deposit on the back-end-of-the-line (BEOL) structures, consisting of highly cross-linked fluorocarbon polymers on the trench sidewalls and potentially metallic or hardmask species that resist purely organic oxidation . To address this, the wet stripping phase employs specialized chemical compositions that utilize oxidizers to break down the polymeric networks and chelating agents to dissolve metallic trace residues into a soluble state . The core chemical logic depends on differential dissolution rates; the wet clean chemistry must selectively remove the hardened residues without attacking the exposed dielectric surfaces or penetrating the porous matrix of the inter-level dielectric (ILD) . Material and method selection for this step is governed by the delicate balance between cleaning efficiency and dielectric preservation . For advanced BEOL interconnects incorporating low-k dielectrics, conventional solvent-based or highly aggressive alkaline chemistries are often unsuitable because they can absorb into the pores of the ILD, thereby increasing the dielectric constant and degrading the material's mechanical strength [A2, P4]. Consequently, modern stripping compositions are formulated with buffering agents and specific corrosion inhibitors that modulate the local pH and selectively passivate vulnerable surfaces during the residue oxidation process . The interaction of process parameters must be tightly controlled; for instance, reducing the plasma ashing power minimizes isotropic oxygen radical diffusion into the ILD sidewalls, mitigating plasma-induced carbon depletion . Correspondingly, the wet clean temperature and oxidizer concentration are optimized to ensure complete removal of sidewall polymers without unintentionally etching the dielectric trench profile, which would otherwise enlarge the physical dimensions of the hybrid bond pad . At the 40nm technology node, shrinking device dimensions drastically reduce the tolerance for changes in critical dimensions and damage to device elements . In the context of DBI, the final hybrid bonding mechanism relies initially on van der Waals forces and subsequent covalent bond formation between plasma-activated, planarized dielectric surfaces . If the ashing and cleaning step induces micro-roughening, chemical depletion, or leaves localized polymeric contaminants, the subsequent chemical-mechanical polishing (CMP) step will yield an imperfect dielectric surface, severely compromising the interfacial bonding strength and alignment accuracy of the heterogeneous integration stack [P1, A1]. Therefore, this process serves not only as an integration bridge to via lithography but as a foundational quality gate for the final 3D interconnect reliability .

[High] Low-k Dielectric Degradation (Plasma Damage & Chemical Absorption): Driven by the diffusion of highly reactive oxygen radicals during plasma ashing or the penetration of wet stripping solvents into the porous matrix of the ILD [P4, A2]. This physical intrusion modifies the chemical structure of the dielectric—often depleting carbon—which simultaneously increases the localized dielectric constant (RC delay penalty) and degrades the mechanical strength required to withstand subsequent CMP stresses [P4, A2].
[Medium] Incomplete Polymer Residue Removal: Caused by insufficient oxidizer activity in the wet chemistry or inadequate thermal activation during the strip process, leaving highly cross-linked post-plasma etch residues adhered to the trench sidewalls . These remaining residues create non-planar topography that disrupts the uniform spin-coating of photoresist for the subsequent Via 7 lithography, leading to depth-of-focus issues and systematic pattern transfer defects .
[Medium] Critical Dimension (CD) Enlargement: Triggered when the selected cleaning formulation or an overly aggressive dry ash isotropically etches the exposed ILD material along the trench sidewalls . Because hybrid bonding architectures rely on sub-micron pitches, even marginal lateral expansion of the trench reduces the physical dielectric spacing between adjacent copper pads, increasing the probability of electrical shorting and cross-talk .

In the process flow for a 40nm BSI CMOS Image Sensor, this specific As

[High] Low-k Dielectric Degradation (Plasma Damage & Chemical Absorption): Driven by the diffusion of highly reactive oxygen radicals during plasma ashing or the penetration of wet stripping solvents into the porous matrix of the ILD [P4, A2]. This physical intrusion modifies the chemical structure of the dielectric—often depleting carbon—which simultaneously increases the localized dielectric constant (RC delay penalty) and degrades the mechanical strength required to withstand subsequent CMP stresses [P4, A2].
[Medium] Incomplete Polymer Residue Removal: Caused by insufficient oxidizer activity in the wet chemistry or inadequate thermal activation during the strip process, leaving highly cross-linked post-plasma etch residues adhered to the trench sidewalls . These remaining residues create non-planar topography that disrupts the uniform spin-coating of photoresist for the subsequent Via 7 lithography, leading to depth-of-focus issues and systematic pattern transfer defects .
[Medium] Critical Dimension (CD) Enlargement: Triggered when the selected cleaning formulation or an overly aggressive dry ash isotropically etches the exposed ILD material along the trench sidewalls . Because hybrid bonding architectures rely on sub-micron pitches, even marginal lateral expansion of the trench reduces the physical dielectric spacing between adjacent copper pads, increasing the probability of electrical shorting and cross-talk .

40nm BSI CMOS Image SensorPreview

Process Cross-Section

Step highlight

In depth

Risks & Challenges

40nm BSI CMOS Image SensorPreview

Process Cross-Section

Step highlight

In depth

Risks & Challenges