Final Oxide CMP removes excess oxide and achieves planarization to enable DBI on the wafer surface .
Following the planarization of the bulk copper and the Ta-based liner, the Final Oxide Chemical Mechanical Planarization (CMP) step prepares the wafer surface for Direct Bond Interconnect (DBI) [P
3]. In a nanoscale Back-Side Illuminated (BSI) CMOS Image Sensor integration flow, this step ensures an ultra-smooth and highly planar dielectric surface necessary for subsequent CIS and ISP wafer bond pairing . The hybrid bonding process requires sub-nanometer surface roughness to facilitate spontaneous van der Waals bonding upon RF surface activation . Furthermore, this step serves to correct residual topography, such as metal dishing or dielectric erosion, which are inherent side effects of the preceding copper and barrier CMP steps . By defining the final dielectric thickness precisely, this step ensures optimal capacitive coupling and mechanical stability for the bonded device . The fundamental material removal mechanism during dielectric CMP is governed by a synergistic combination of chemical surface modification and mechanical abrasion . The process hydrodynamics and mechanical removal rate can be modeled by Preston's equation, where the removal rate is proportional to the applied downforce pressure and the relative velocity between the wafer and the polishing pad . Chemically, the alkaline slurry promotes the hydration of the silicon dioxide surface, forming a softer, chemically reactive silanol layer . This softened passivating layer is then mechanically sheared away by abrasive particles, continuously exposing fresh oxide for further reaction . To ensure precise control over the final dielectric thickness without relying solely on timed polishes, in-situ optical metrology is often employed . This technique utilizes broadband spectral reflection and multilayer interference models to monitor the film thickness in real time, despite the presence of complex media like slurry and polishing pads . The selection of slurry chemistry and abrasive types is critical to minimize defectivity, which is paramount for successful wafer bonding . Colloidal silica abrasives are frequently used, but they are prone to aggregation under shear stress, forming large particles that cause severe micro-scratches . To mitigate this, nonionic dispersants can be introduced into the slurry to provide steric stabilization, thereby improving colloidal stability and significantly reducing scratch counts . Additionally, in-situ slurry separation and filtration systems can be integrated into the CMP apparatus to continuously remove polishing debris and oversized agglomerates . Control parameters such as retaining ring pressure, platen speed, and slurry flow rate are optimized to balance the removal rate against the risk of creating localized stress concentrations that lead to dielectric tearing or scratching . In the context of 40nm technology nodes, the scaling of interconnect line widths and spacing significantly alters the local contact mechanics and slurry transport dynamics during CMP . As pattern density increases, the risk of layout-dependent non-uniformities, such as metal dishing, becomes more pronounced, which can directly reduce the conductive cross-sectional area and degrade the electrical performance of the interconnects . For advanced CMOS image sensors, maintaining uniform interconnect electrical characteristics is essential to support high-speed signal readout and minimize spatial noise variations across the pixel array . Therefore, the Final Oxide CMP step must employ highly selective polishing conditions or specialized dielectric-on-dielectric stopping mechanisms to achieve global planarization across the dense nanoscale interconnect structures without compromising the integrity of the underlying copper layers (Engineering Practice).
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