Ashing & Strip/Clean - 40nm

Ashing and strip/clean processes remove residual photoresist, BARC, and CFx polymers from DBI surfaces to enable subsequent bonding without contamination .

Following the ILD 6-1 Etch, the final trench and via cavities for the Direct Bond Interconnect (DBI) are defined, but the surfaces remain hea

vily contaminated with residual photoresist, bottom anti-reflective coating (BARC), and highly crosslinked fluorocarbon (CFx) polymeric etch residues . This specific Ashing & Strip/Clean step is critical because it serves as the final surface preparation before Ta-based liner and copper seed deposition, distinguishing it from earlier intermediate cleans that only remove bulk resist between partial etches . This step demands absolute residue removal at the via bottom to ensure void-free electrochemical plating and optimal contact resistance with the underlying conductive layer, consistent with the requirements for pristine interconnect interfaces [A1, A2]. Furthermore, for DBI technology, maintaining the structural integrity of the dielectric top corners is essential, as any degradation will cause non-planarity during subsequent chemical mechanical planarization (CMP) and fundamentally compromise the hybrid bonding interface . The removal process must meticulously decouple the elimination of highly crosslinked organic residues from the structural degradation of the underlying porous low-k dielectric . Traditional oxygen plasma ashing relies on reactive radicals that readily penetrate the high-specific-surface-area porous low-k network, breaking weak Si-CH3 bonds, initiating carbon loss, and forming hydrophilic Si-OH groups that severely degrade the dielectric constant (k-value) . To circumvent this, advanced strip mechanisms employ ultraviolet (UV) irradiation to induce photochemical chain scission within the fluoropolymer backbone . This localized UV photon energy selectively breaks C-C and C-F bonds, reducing the crosslink density and introducing polar groups without subjecting the delicate low-k framework to high-energy ion bombardment . Following this structural modification, organic solvents formulated with reactive components penetrate the loosened polymer network, selectively dissolving the photoresist and swelling the residues to achieve complete interfacial delamination . The integration of a UV-assisted or all-wet clean is necessitated by the inability of conventional aqueous mixtures, such as dilute HF, to remove the fluorinated crust without unacceptably etching the dielectric and causing critical dimension loss . Solvents containing specific functional groups are selected for their thermodynamic capability to dissolve ester and lactone groups in the photoresist while chemically complexing with inorganic etch byproducts like titanium or fluorine . Additionally, megasonic acoustic energy is applied during the wet phase to generate cavitation microjets, which overcome the mass transport limitations inherent to fine, high-aspect-ratio interconnect cavities . Because solvent ingress into the low-k pores can temporarily increase the effective k-value, a subsequent low-pressure, high-temperature bake is carefully integrated into the process flow to volatilize and drive out residual solvents, thereby restoring the intrinsic electrical performance of the dielectric . In nanoscale BEOL architectures, the reduced mechanical and chemical stability of the highly porous low-k materials drastically shrinks the process window for residue removal . If aggressive plasma-based stripping is utilized, the resulting damaged, hydrophilic layer near the trench sidewalls easily absorbs moisture, fundamentally altering the local electronic structure and increasing leakage currents, which degrades device performance as governed by fundamental semiconductor carrier transport principles [T1, P4]. Therefore, utilizing a highly selective modification-and-dissolution scheme is mandatory at this node to prevent low-k undercut and preserve the precise vertical geometry required for subsequent conformal barrier layer deposition [A2, P3].

[High] Low-k Dielectric k-value Degradation: Excessive plasma exposure or failure to adequately bake out penetrating wet solvents causes carbon depletion (loss of Si-CH3) and moisture absorption (formation of Si-OH) within the porous low-k framework . This increases the material's polarity and parasitic capacitance, directly degrading the RC delay of the integrated circuit .
[High] Incomplete Fluorocarbon Residue Removal: Insufficient UV irradiation dose fails to induce adequate photochemical chain scission in the dense, highly crosslinked CFx post-etch crust . As a result, the wet cleaning solvent cannot penetrate or dissolve the residue, leaving polymeric contaminants at the via bottom that drastically increase contact resistance with the underlying conductive structure [P1, A2].
[Medium] Top-Corner Rounding and Non-Planarity: Aggressive chemical attack or an overextended wet strip process selectively weakens the dielectric top corners, especially in regions previously damaged by hard mask etching . This structurally compromised region erodes easily, resulting in non-planar surfaces that critically cause voiding or failure in the final DBI hybrid bonding interface .
[Medium] Pattern Collapse or Mechanical Damage: High-intensity megasonic power used to assist mass transport in deep, high-aspect-ratio cavities generates overly aggressive acoustic cavitation events . The resultant microjets impart mechanical stress that exceeds the yield strength of the highly porous, mechanically weakened low-k dielectric walls, leading to physical fracture or structural collapse .

Ashing and strip/clean processes remove residual photoresist, BARC, and CFx polymers from DBI surfaces to enable subsequent bonding without contamination .

Following the ILD 6-1 Etch, the final trench and via cavities for the Direct Bond Interconnect (DBI) are defined, but the surfaces remain hea

[High] Low-k Dielectric k-value Degradation: Excessive plasma exposure or failure to adequately bake out penetrating wet solvents causes carbon depletion (loss of Si-CH3) and moisture absorption (formation of Si-OH) within the porous low-k framework . This increases the material's polarity and parasitic capacitance, directly degrading the RC delay of the integrated circuit .
[High] Incomplete Fluorocarbon Residue Removal: Insufficient UV irradiation dose fails to induce adequate photochemical chain scission in the dense, highly crosslinked CFx post-etch crust . As a result, the wet cleaning solvent cannot penetrate or dissolve the residue, leaving polymeric contaminants at the via bottom that drastically increase contact resistance with the underlying conductive structure [P1, A2].
[Medium] Top-Corner Rounding and Non-Planarity: Aggressive chemical attack or an overextended wet strip process selectively weakens the dielectric top corners, especially in regions previously damaged by hard mask etching . This structurally compromised region erodes easily, resulting in non-planar surfaces that critically cause voiding or failure in the final DBI hybrid bonding interface .
[Medium] Pattern Collapse or Mechanical Damage: High-intensity megasonic power used to assist mass transport in deep, high-aspect-ratio cavities generates overly aggressive acoustic cavitation events . The resultant microjets impart mechanical stress that exceeds the yield strength of the highly porous, mechanically weakened low-k dielectric walls, leading to physical fracture or structural collapse .

40nm BSI CMOS Image SensorPreview

Process Cross-Section

Step highlight

In depth

Risks & Challenges

40nm BSI CMOS Image SensorPreview

Process Cross-Section

Step highlight

In depth

Risks & Challenges