This process step utilizes photolithography to define the implantation windows for the P-Well in the periphery region of a 40nm BSI CMOS Image Sensor P2.In modern image sensors, the periphery circuits handle high-speed signal processing, timing control, and readout logic, which require standard CMOS transistor architectures P2.This step follows the Pixel Array P-Well formation and its subsequent strip/clean processes, isolating the logic well definition from the specialized pixel well integratio