40nm BSI CMOS Image SensorPreview

ccessfully blocked high-energy dopants from entering the complementary N-Well regions [P2]. This photoresist must be completely stripped to restore a pristine semiconductor surface before applying the next photolithography layer for the Periphery N-Well Contact IIP [P1]. Unlike simple photoresist stripping operations used after non-implanting steps, this specific well-module strip faces the complex challenge of removing an ion-implanted photoresist [P1]. During the preceding implantation, energetic ions bombard the resist surface, driving out hydrogen and leaving behind a hardened, highly crosslinked carbon-rich crust [P4]. Complete and damage-free removal of this composite organic layer is critical, as any residual polymeric micro-masking would disrupt the precise spatial doping profiles required for the 40nm CMOS image sensor periphery logic devices [A3]. The physical mechanism of this process typically relies on a two-stage dry ashing and wet cleaning sequence (Engineering Practice). During the plasma ashing phase, microwave or radio-frequency energy excites feed gases to generate a high density of chemically reactive radicals [P1]. For example, in optimized plasma chemistries, reactive species such as atomic oxygen (O) and hydroxyl radicals (OH) diffuse to the wafer surface and react with the organic polymer matrix, breaking stable C–C and C–H bonds [P1]. These radical-driven reactions oxidize the carbonaceous resist into volatile species, primarily carbon monoxide (CO) and carbon dioxide, which are subsequently exhausted by the vacuum system [P1]. Because the hardened resist crust is highly susceptible to further thermal crosslinking, conventional high-temperature ashing can inadvertently transform the resist into an intractable residue [P4]. To prevent this, the process leverages low-temperature, radical-dominated plasma regimes—often operating at elevated chamber pressures—which maximize chemical collision frequencies while minimizing destructive physical ion sputtering [P1]. Material and method selection for this step focuses on balancing rapid stripping kinetics with strict substrate preservation [A1]. Conventional high-temperature oxygen plasmas are often avoided here because excessive thermal loads exacerbate resist hardening, rendering the residues highly resistant to downstream chemical treatments [P4]. Instead, processes may incorporate molecular additives, such as water vapor, to lower the activation energy of the ashing reaction and supply abundant OH radicals, which efficiently volatilize hardened polymers at substantially lower wafer temperatures [P1]. Following the dry ash, a targeted wet chemical clean is deployed to dissolve remaining organometallic complexes and particulate contaminants [A1]. The wet clean formulation typically employs selective oxidizers and chelating agents that capture liberated metallic impurities without excessively etching the exposed shallow trench isolation (STI) oxides or roughening the bare active silicon areas [A1]. At the 40nm technology node, the periphery circuits of a BSI CMOS image sensor demand extremely tight control over threshold voltage variability, which is highly sensitive to surface defect states [P2]. Uncontrolled plasma exposure during the strip process can introduce trap states at the silicon-dielectric interfaces or embed uncompensated charges in adjacent isolation structures, fundamentally altering local electrostatics [T1]. Therefore, ensuring that the plasma ashing operates in a chemically driven, low-ion-energy mode is essential to clear the post-implantation crust without degrading the sub-threshold characteristics and carrier mobility of the highly scaled periphery logic transistors [P1].