The patterned photoresist will serve as a physical implantation mask, ensuring that the subsequent p-type dopants (such as boron) are introduced exclusively into the targeted periphery NMOS regions .
This process step utilizes photolithography to define the implantation windows for the P-Well in
the periphery region of a 40nm BSI CMOS Image Sensor . In modern image sensors, the periphery circuits handle high-speed signal processing, timing control, and readout logic, which require standard CMOS transistor architectures . This step follows the Pixel Array P-Well formation and its subsequent strip/clean processes, isolating the logic well definition from the specialized pixel well integration . While the pixel array often utilizes deep P-wells to establish an electrostatic shield that prevents charge leakage into unrelated N-wells, the periphery P-well is optimized purely for standard NMOS threshold voltage control and punch-through prevention . The patterned photoresist will serve as a physical implantation mask, ensuring that the subsequent p-type dopants (such as boron) are introduced exclusively into the targeted periphery NMOS regions . The physical mechanism of this step relies on the precise transfer of geometric patterns onto a photosensitive polymer layer via optical lithography . The photoresist is applied via a spin-coating process, pre-baked to drive off solvents, exposed to UV light projected through a photomask, and finally developed with a chemical developer to clear the target implantation zones . Because the 40nm node involves dense layouts, lithographic resolution is fundamentally constrained by Rayleigh's criterion, often requiring optical proximity correction (OPC) to mitigate systematic pattern distortion caused by the interference of neighboring light and dark fields . Once developed, the remaining photoresist acts as a stopping layer against high-energy ions . The thickness of the resist is engineered to exceed the projected range and straggle of the implant ions, preventing dopant penetration into adjacent structures such as periphery N-wells . Photoresist is selected as the optimal masking material because it can be processed at low temperatures and subsequently stripped without inflicting mechanical or thermal damage to the underlying silicon substrate . The geometric fidelity of this mask directly influences the spatial boundaries of the implanted well, which governs the lateral diffusion profile during subsequent annealing steps . Edge placement precision is critical, as the MOSFET threshold voltage is highly sensitive to the exact doping concentration and the depletion layer width formed at the boundaries of these wells . Furthermore, separating the periphery P-well mask from the pixel array P-well mask allows engineers to independently tune the implant conditions (ion species, dose, and kinetic energy) for the logic NMOS devices without compromising the sensitive full-depletion requirements of the active pixel matrix .
Sign in to continue through all 417 steps