The complete removal of the resist without inducing interface states ensures that the subsequent NMOS VT Adjust implant accurately targets the channel surface, maintaining proper threshold voltage control across the periphery devices .
Following the high-dose N-Well Contact IIP, the photoresist m
ask must be completely removed before proceeding to the NMOS VT Adjust lithography . During the contact implant, the resist absorbs a massive dose of energetic N-type ions, transforming its upper layer into a heavily cross-linked, carbonized crust known as High-Dose Ion-implanted Photoresist (HDI-PR) . If this hardened crust and the underlying bulk resist are not entirely eradicated, residual organics will severely degrade the coatability and overlay alignment of the subsequent NMOS VT Adjust photoresist . Furthermore, incomplete removal would locally block the VT adjust implant, causing massive threshold voltage variations in the logic transistors . Thus, this specific ashing step is distinctly engineered to tackle the mechanically toughened HDI-PR crust , setting it apart from standard, non-implanted resist stripping operations (Engineering Practice). The removal of HDI-PR relies on a dual-action mechanism involving reactive radical oxidation and chemical dissolution . Standard ashing generates reactive oxygen and hydroxyl species via plasma excitation, which attack the polymeric backbone of the resist . For highly carbonized crusts, purely physical dry ashing can induce excessive thermal stress or plasma damage to the underlying silicon substrate, mimicking the plasma-induced defect generation observed in high-k/metal gate integrations . To circumvent this, advanced processes often employ a radical-driven, low-ion-energy ashing mechanism, such as microwave-excited plasma that dissociates water vapor into chemically active OH, O, and H radicals . These species react with the organic photoresist to break C-C and C-H bonds, converting the carbon into volatile byproducts like CO . The process is highly transient; at plasma ignition, oxygen-containing radicals are rapidly consumed by the resist surface, temporarily depleting gas-phase OH and O densities while increasing CO emission . Wet strippers alone struggle to penetrate the hardened crust of HDI-PR due to its drastically altered surface hardness and elastic modulus . Conversely, aggressive dry plasma ashing can cause surface charging and localized lattice damage . Therefore, hybrid approaches such as plasma liquid-vapor activation (PLVA) are utilized to introduce high-energy radicals that lower the apparent activation energy of the stripping reactions without direct ion bombardment on the wafer . By carefully controlling the applied activation voltage or microwave power, the concentration of active species is maximized while avoiding activity saturation or side reactions . Additionally, maintaining a moderately high operating pressure enhances three-body collisions and radical densities, favoring chemical oxidation over physical sputtering and thereby ensuring a damage-free clean . At the 40nm node, the tolerance for substrate silicon loss and surface roughening is extremely stringent, as even sub-nanometer variations can perturb the short-channel electrostatics described by constant electric field scaling theory . Therefore, low-temperature, radical-dominant ashing is preferred to suppress thermal degradation and unwanted dopant diffusion (Engineering Practice). The complete removal of the resist without inducing interface states ensures that the subsequent NMOS VT Adjust implant accurately targets the channel surface, maintaining proper threshold voltage control across the periphery devices .
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