In the CMOS process flow, the fabrication of a high-performance MOSFET relies fundamentally on establishing a near-ideal interface between the silicon channel and the gate dielectric T1.Following the high-energy ion implantations used for well formation and threshold voltage adjustment, the uppermost layers of the silicon substrate invariably suffer from lattice damage and embedded contaminants A1.To remediate this, a sacrificial oxidation step is previously performed to deliberately consume the