In the fabrication of a 40nm Backside Illuminated (BSI) CMOS Image Sensor, the Lower Vertical Grid module provides optical isolation between adjacent pixels to prevent optical crosstalk A2.Following the deposition of the barrier layer and the bulk tungsten (W) fill, a thick W overburden remains on the wafer surface A1.The W Chemical Mechanical Planarization (CMP) step is introduced precisely at this point to remove this conductive overburden and isolate the individual grid structures P1.By stopp