A multilayer resist scheme creates a temporary polymer mask template for subsequent optical pad 1 etch and oxide grid seal layer etch steps .
In depth
The "Lower Vertical Grid Trench - Photo" step defines the precise geometric boundaries for optical and electrical isolation structures between adjacent pix
els in a nanoscale Backside Illuminated (BSI) CMOS Image Sensor (Engineering Practice). Following the Pre Litho Cleaning and Optical Pad 1 Deposition steps, this photolithography process creates the temporary polymer masking template required for the subsequent Optical Pad 1 Etch and Oxide Grid Seal Layer Etch steps . Unlike Shallow Trench Isolation (STI) which electrically isolates active front-end transistor regions, or Metal Trench lithography which defines metallic electrical routing paths, this step specifically patterns a high-aspect-ratio barrier matrix designed to suppress optical and lateral carrier crosstalk between adjacent backside photodiodes . The spatial precision of this patterned grid is paramount, as the width and placement of the trench directly govern the effective fill factor and quantum efficiency of the image sensor (Engineering Practice). The physical mechanism of this step relies on optical lithography to transfer a reticle pattern into a photosensitive resist film coated over the wafer . The fundamental resolution limit of this imaging process is governed by the Rayleigh criterion, mathematically expressed as R = k_1 \frac{\lambda}{NA}, which dictates the minimum resolvable feature size based on the exposure wavelength (λ) and the numerical aperture (NA) of the lens system . Upon exposure to deep ultraviolet light, photoacid generators within a chemically amplified positive resist undergo a photochemical reaction to yield acid, which subsequently catalyzes the cleavage of solubility-inhibiting polymer groups during a post-exposure bake . This reaction converts the spatial aerial image intensity into a stark solubility contrast, allowing a liquid developer to preferentially wash away the exposed regions and reveal the underlying optical pad layer . To counteract optical diffraction-induced distortions such as corner rounding and line-end shortening, elaborate mathematical Optical Proximity Correction (OPC) is applied to reshape the photomask patterns . For a narrow nanoscale isolation trench, 193-nm immersion lithography (193i) is typically selected because introducing a purified liquid medium between the lens and the wafer increases the effective numerical aperture, enabling the resolution of tighter pitches without the prohibitive costs of extreme ultraviolet (EUV) systems . A multilayer resist scheme, such as a trilayer system combining a high-resolution photoresist, a silicon-containing hardmask, and a planarizing bottom anti-reflective coating, is heavily utilized to smooth underlying substrate topography and prevent standing waves caused by reflections from the high-index optical pad layers . Process parameters such as exposure dose and focus depth are tightly coupled; an increased photon dose will widen the trench critical dimension (CD) in a positive resist but simultaneously narrows the permissible focus window (Engineering Practice). The strict control of these interrelated parameters ensures that overlay mismatches with the underlying photodiode arrays do not degrade device reliability or yield . At the 40nm technology node, the physical pixel dimensions closely approach the wavelength of incident visible light, making the physical suppression of optical diffraction and crosstalk acutely challenging . To maximize the light-capturing photosensitive area, the grid trench width must be minimized, driving the immersion lithography process to its absolute physical limits . At these extreme dimensions, the thermodynamic and statistical physics of the photoresist manifest as Line Edge Roughness (LER), a defect driven by the discrete graininess of the polymer and stochastic variations in photon absorption . Consequently, advanced Design for Manufacturing (DFM) strategies and rigorous process monitoring must be integrated to predict and compensate for systematic variations, ensuring the trench sidewalls remain perfectly straight to avoid arbitrary optical scattering within the finished sensor .
Risks & Challenges
[High] Overlay Error: Discrepancies in scanner alignment or overlay mismatches between the lithographic pattern and previously formed features can shift the grid position . This directly causes asymmetric optical crosstalk or physical encroachment into the active photodiode area, degrading image sensor performance (Engineering Practice).
[High] Line Edge Roughness (LER): Stochastic variations in photon arrival and photoresist deprotection cause waviness along the developed resist edges . When transferred into the underlying pad layers during the subsequent etch, these rough sidewalls induce localized optical scattering and degrade the isolation efficiency of the trench .
[Medium] Incomplete Resist Clearance (Scumming): Insufficient exposure dose or focal plane deviation prevents the complete chemical dissolution of the positive photoresist at the trench bottom . This leaves a residual polymer film that acts as a micro-mask during the subsequent Optical Pad Etch, resulting in blocked or shallow trenches .
[Low] Depth of Focus (DOF) Margin Failure: Variations in underlying topography or inadequate planarization by the multilayer resist system can cause the photoresist surface to exceed the limited depth of focus of high-NA immersion lithography . This blurring of the aerial image leads to bridging between adjacent trench patterns, destroying the continuous pixel isolation grid (Engineering Practice).