40nm BSI CMOS Image SensorPreview

al Pad 2 Deposition establishes a critical optical and structural interface [A2]. Unlike Optical Pad 1, which typically acts as a base layer beneath the light shield grid, or Optical Pad 3, which interfaces with top-level micro-lenses or color filters, Pad 2 is specifically positioned to bridge the polished tungsten (W) grid and the incoming Lower OCL (On-Chip Lens) Planar Layer (Engineering Practice). Its primary structural role is to seal the exposed tungsten from oxidation, while its fundamental optical role is to serve as a finely tuned index-matching layer that minimizes Fresnel reflections between the high-index grid structures and the overlying planarizing materials [P3]. The physical mechanism of this step relies on Plasma Enhanced Chemical Vapor Deposition (PECVD) to grow a highly controlled silicon oxynitride (SiOxNy) network [P1]. In a low-pressure RF plasma environment, high-energy electrons collide with reactive precursors such as SiH4, N2O, and NH3, dissociating them into highly reactive radicals and ions [P2]. Because the RF electric field creates a non-equilibrium plasma where the electron temperature far exceeds the substrate temperature, dense dielectric layers can be deposited at relatively low thermal budgets [P1]. This low-temperature characteristic is strictly required to prevent thermal diffusion, stress relaxation, or interface degradation in the underlying CMOS devices and metal grids [P1]. Silicon oxynitride is explicitly selected for this optical pad because its chemical composition and resulting optical properties can be continuously tuned [P2]. During the surface reaction, the competitive formation of Si-O and Si-N bonds is directly controlled by the gas flow ratios; increasing the proportion of nitrogen-containing radicals suppresses Si-O formation and increases the refractive index (n) [P2]. By precisely engineering the refractive index and the extinction coefficient (k), this layer acts analogously to an inorganic bottom anti-reflective coating (BARC) [P3]. The chosen thickness and optical constants establish a phase cancellation mechanism, ensuring that light reflected from the Pad/OCL interface undergoes destructive interference with surface-reflected light [P3]. Furthermore, RF power and chamber pressure are carefully balanced to modulate the particle mean free path, optimizing film density and mechanical stress to ensure robust adhesion to the heterogeneous W/oxide post-CMP surface [P1]. At the nanoscale Backside Illumination (BSI) node, pixel dimensions scale to near or below the wavelength of visible light, meaning any unmitigated interface reflection directly translates to severe optical crosstalk or quantum efficiency loss [P3]. In addition to enhancing final sensor optical performance, this precisely tuned SiON layer provides critical lithographic control for the subsequent Sacrificial Lower OCL step; by minimizing substrate reflectivity, it drastically reduces standing waves and critical dimension (CD) swing during the resist exposure phase [P3].