Within the polishing slurry, oxidizers such as hydrogen peroxide chemically react with the tungsten surface to form a passivating tungsten oxide reaction layer .
In depth
In the fabrication of a nanoscale Backside Illuminated (BSI) CMOS Image Sensor, the Lower Vertical Grid module provides optical isolati
on between adjacent pixels to prevent optical crosstalk . Following the deposition of the barrier layer and the bulk tungsten (W) fill, a thick W overburden remains on the wafer surface . The W Chemical Mechanical Planarization (CMP) step is introduced precisely at this point to remove this conductive overburden and isolate the individual grid structures . By stopping on the underlying dielectric layer, the CMP process creates inlaid metal features that are electrically and optically separated . Furthermore, the resulting high-planarity surface is essential for the subsequent Post CMP Cleaning and the deposition of planar optical layers, such as the Optical Pad and Lower On-Chip Lens (OCL) layers . If significant topography were left behind, the first interconnected optical or metal level would be adversely affected, leading to critical performance degradation in the imaging array . The fundamental physical and chemical mechanism of W CMP relies on the synergistic action of chemical softening and mechanical shear . Within the polishing slurry, oxidizers such as hydrogen peroxide chemically react with the tungsten surface to form a passivating tungsten oxide reaction layer . This oxidized layer possesses significantly reduced mechanical strength compared to the bulk metallic tungsten, making it easily removable . Under the applied load of the polishing head, relative motion between the polishing pad and the wafer causes abrasive particles in the slurry to selectively shear off this passivated layer . By tightly controlling the balance between the chemical reaction kinetics forming the oxide and the contact mechanics removing it, the process avoids purely isotropic chemical corrosion and minimizes pure mechanical scratching . This dynamic equilibrium allows the CMP process to achieve a high removal rate for the W overburden while maintaining low defect densities on the final surface . The selection of materials and polishing methods for W CMP is heavily dictated by the need to manage multi-material interfaces, specifically the tungsten fill, the Ti/TiN liner, and the underlying dielectric . The Ti/TiN liner is utilized to improve W adhesion and act as a diffusion barrier, but it must be completely removed from the field areas during CMP to prevent electrical shorting . Modern W CMP often employs silica-based slurries with hydrogen peroxide, which tend to have lower selectivity between W and the liner, allowing for a single-step removal process . However, this process must be carefully tuned regarding applied load and rotational speed; otherwise, differences in removal rates can lead to severe dishing of the tungsten or erosion of the softer surrounding dielectric . Furthermore, the CMP process inherently generates nanoscale tungsten particles that can remain in recesses or on the surface . These nano-sized particles are highly problematic for yield and are extremely difficult to detect using standard optical bright-field or dark-field methods due to weak optical contrast at the nanometer scale . At the 40nm technology node for BSI CIS devices, the demands on global and local planarization are exceedingly stringent because optical stack performance and subsequent high-numerical-aperture lithography are highly sensitive to depth-of-field variations . Tighter focus requirements necessitate that the processed wafers be entirely planarized . Moreover, CMP processes can cause asymmetrical distortion of coarse alignment gratings, resulting in large alignment offsets during subsequent lithography steps . Therefore, the W CMP process parameters must be co-optimized not only for local step height reduction but also to preserve the geometric integrity of critical alignment marks . A subsequent buffing step is sometimes employed to further improve planarity and lower the final defect counts before entering the post-CMP cleaning module .
Risks & Challenges
[High] Tungsten Dishing and Dielectric Erosion: Differences in the chemical-mechanical removal rates between the softer dielectric, the barrier liner, and the W plug lead to local topography variations . Excessive dishing of the W grid or erosion of the surrounding oxide creates non-planar surfaces that directly degrade the depth-of-field margin for subsequent optical lithography .
[High] Nanoscale Tungsten Particle Contamination: The abrasive and chemical nature of the W CMP process generates nanoscale tungsten particles that can adhere to the dielectric surface or become trapped in micro-recesses . Because these particles exhibit extremely weak optical contrast against the dielectric, they often escape standard optical defect inspection and can cause severe optical scattering or electrical shorts in the CIS pixel array .
[Medium] Asymmetrical Alignment Mark Distortion: The mechanical shear forces applied during CMP can cause asymmetric deformation of alignment gratings used for lithography . This distortion disrupts the diffraction signals used by optical metrology sensors, resulting in sub-nanometer overlay errors that are critical at the 40nm node .
[Medium] Incomplete Barrier Liner Removal: If the slurry selectivity is not optimized, residual Ti/TiN barrier liner material may remain on the dielectric field between W grid lines . This conductive residue creates stringers that cause fatal shorting problems across the interconnected grid structures .
[Low] Precipitation of Tungsten Oxides: When using silica-based slurries containing oxidizers, chemical byproducts can precipitate into circular tungsten oxide defects on the wafer surface . These defects act as optical blockers or structural flaws unless thoroughly removed by utilizing strong ammonia solutions in the subsequent post-polish cleaning step .