40nm BSI CMOS Image SensorPreview

backside are highly reactive and susceptible to metallic contamination [P4]. The LS/Aperture Grid Barrier Deposition step deposits a conformal refractory metal/metal-nitride stack (typically Ti/TiN) to line these backside trenches and contact holes before the bulk Light Shield (LS) / Aperture Grid metal is deposited [A1]. This step is distinct from the front-end Ta-based Bottom Barrier, which is optimized for sub-micron Cu interconnects in the CMOS logic routing, and different from the Lower Vertical Grid Barrier, which lines deeper optical isolation structures within the pixel [A2]. By lining the backside grid trenches, this barrier prevents the bulk grid metal from diffusing into the photoactive silicon layer and provides an adhesive transition layer for the subsequent bulk metal fill [P2]. The core physical mechanism of this step relies on establishing a structurally dense, chemically stable nitride layer that suppresses solid-state interdiffusion [P2]. Metal diffusion into semiconductors primarily proceeds along grain boundaries and point defects, governed by thermally activated hopping models where the diffusion coefficient follows an Arrhenius relationship [P1]. In columnar polycrystalline barrier films, abundant grain boundaries act as low-energy diffusion channels that significantly reduce the activation energy for diffusion [P1]. To counter this, reactive sputtering or chemical vapor deposition (CVD) is employed to introduce nitrogen into the lattice, effectively "stuffing" defects and reducing the number of available diffusion pathways [P2]. Additionally, ionized metal plasma (IMP) techniques can be utilized to impart directional kinetic energy to the deposited metallic species in an electric field, greatly enhancing bottom coverage in high-aspect-ratio grid trenches [P4]. The selection of a Ti/TiN stack is driven by both electrical and metallurgical requirements [P3]. The initial thin titanium layer ensures robust adhesion to the surrounding dielectric and forms a low-barrier Ohmic contact with the exposed silicon, governed by the metal-semiconductor work function difference and interfacial energy band alignment [T1]. The subsequent titanium nitride layer is favored for its strong Ti–N mixed covalent/ionic bonding, high melting point, and excellent chemical stability [P2]. Parameter tuning during reactive sputtering, such as adjusting the nitrogen-to-argon ratio, directly impacts the film's stoichiometry and defect density [P3]. High nitrogen flow favors the formation of stoichiometric or slightly N-rich TiN, which exhibits superior thermal stability and blocks metal spiking more effectively than Ti-rich films [P2]. Furthermore, optimizing these deposition conditions helps minimize grain boundary defect density and reduces carrier scattering, thereby lowering the overall contact resistance of the optical grid structure [P3]. In a nanoscale Backside Illuminated (BSI) CMOS Image Sensor flow, the spatial constraints of the pixel pitch demand extremely conformal deposition in narrow optical isolation trenches (Engineering Practice). Because the barrier layer directly interfaces with the silicon where photogenerated carriers are collected, any localized junction leakage or deep-level defect formation resulting from barrier failure will manifest as unacceptable dark current or white pixels [P4]. Therefore, the deposition technique must balance excellent step coverage—often achieving high conformality via CVD TiN [P4]—with a strictly controlled thermal budget to prevent the subthreshold leakage degradation of the already integrated front-end logic devices [T2].