40nm BSI CMOS Image SensorPreview

rgo a Pre Litho Cleaning step before the Lower Vertical Grid Trench photoresist application [P4]. This step is distinct from other pre-litho cleans because it specifically prepares an optical pad dielectric surface for a high-aspect-ratio trench patterning process, which is critical for optical isolation in 40nm BSI CMOS image sensors [P3]. The primary objective is to remove any adventitious airborne contaminants, particles, or trace chemical residues left from the preceding deposition steps, ensuring a pristine surface for photoresist or bottom anti-reflective coating (BARC) adhesion [P2]. A clean interface is essential to prevent lithographic defects such as resist peeling or pattern collapse during the subsequent photolithography steps [A1]. The cleaning process typically employs standard wet chemical mixtures, such as Standard Clean 1 (SC1) containing ammonium hydroxide and hydrogen peroxide, or Standard Clean 2 (SC2) containing hydrochloric acid and hydrogen peroxide [A2]. The SC1 solution relies on concurrent oxidation and dissolution mechanisms, where H2O2 oxidizes trace organic contaminants and the underlying surface, while the alkaline NH4OH mildly etches the oxidized surface to undercut and lift off particulate matter [A3]. This wet-chemical interaction must be carefully balanced to prevent excessive roughening of the optical pad layer, conceptually similar to the controlled oxidation and dissolution principles utilized in wet-chemical atomic layer etching to maintain smooth surfaces [P1]. Furthermore, for specialized dielectric or polymeric materials, modern processing solutions incorporating organic solvents and trace metal ions can be used to selectively remove residues without causing chemical attack or structural swelling [A1]. The selection of chemical ratios, temperature, and exposure time is dictated by the chemical stability of the Optical Pad 1 material and the required defectivity targets (Engineering Practice). If the pad contains sensitive or low-k dielectric materials, strongly alkaline or highly chelating environments might induce unwanted corrosion or porosity changes [A1]. Therefore, diluted chemistries or mild temperature settings are preferred to maintain the optical properties (refractive index and extinction coefficient) of the pad layer, which are critical for maximizing photon collection and minimizing cross-talk in the CIS grid [P2]. In addition, controlling the surface state through a mild oxidation-dissolution cycle ensures that the surface energy is optimized for uniform resist coating, preventing macro-scale dewetting defects [P2]. At the 40nm node for BSI image sensors, the pixel pitch is highly scaled, making the grid trench dimensions extremely critical (Engineering Practice). Any nanometer-scale particle remaining on the surface prior to lithography can act as a micromask, altering the local optical interference during exposure and causing line-width variations in the grid pattern [P2]. Consequently, this Pre Litho Cleaning step requires stringent defectivity control and relies on kinetically controlled surface reactions rather than purely hydrodynamic mechanical forces to dislodge nanoscale contaminants [P1].