The etching process relies on a fluorocarbon-based high-density plasma, where the mechanism is governed by a dynamic balance between physical ion bombardment and chemical polymer passivation .
In depth
In the 40nm BSI CMOS Image Sensor flow, the Oxide Grid Seal Layer Etch is a critical pattern transfer st
ep within the Light Shield Grid (LS_GRID) module . Positioned after the Optical Pad 1 Etch and before the Lower Vertical Grid Barrier Deposition, this step clears the protective oxide seal layer at the bottom of the grid trenches . The primary purpose of this etch is to expose the underlying substrate or primary isolation structure, preparing a pristine, fully opened interface for the subsequent grid barrier and metal or dielectric fill . Unlike general planar oxide or pad oxide etches (such as steps 10 or 118), this step occurs within a high-aspect-ratio trench geometry, requiring strict critical dimension (CD) control to prevent optical crosstalk between adjacent pixels while ensuring a geometry that allows for conformal subsequent depositions . The etching process relies on a fluorocarbon-based high-density plasma, where the mechanism is governed by a dynamic balance between physical ion bombardment and chemical polymer passivation . In this plasma system, fluorine radicals chemically react with the silicon dioxide to form volatile SiFxOy byproducts, while CFx radicals simultaneously form a protective polymer layer on exposed surfaces . Ion bombardment, tightly controlled by the bias power, supplies the directional kinetic energy required to selectively clear this polymer from the horizontal trench bottoms, allowing the chemical etch to proceed anisotropically . The strongly nonlinear coupling between the RF power (driving ion flux) and the gas chemistry (driving reactive radical density) must be precisely modulated to maintain a stable etch rate without causing "etch stop" or "blow out" of the trench profile . Achieving high selectivity to the underlying silicon or nitride stopping layer is essential to avoid catastrophic damage to the active pixel regions . This selectivity is optimized by manipulating the fluorocarbon gas composition and reactor wall temperatures, which modulates the loss and redistribution of fluorocarbon species in the plasma . As reactor wall temperatures increase, the wall acts as a weaker sink for fluorocarbon radicals, keeping their concentration higher in the bulk plasma and promoting preferential polymer deposition on the cooler wafer surface . This deposited polymer effectively suppresses the etch rate of non-oxygen-containing materials like Si or SiN, while SiO2 etching—driven by ion-assisted oxygen release—remains largely uninterrupted, thereby maximizing selectivity . Furthermore, managing the source-to-bias power ratio ensures that the sidewalls remain sufficiently passivated to maintain a highly vertical profile . Smooth, vertical sidewalls are critical because geometric roughness or scalloping can induce severe thermo-mechanical stress, which acts as an initiation point for barrier layer cracking and subsequent electrical leakage during backend thermal cycling . At the 40nm CIS node, pixel pitches approach the optical wavelength limit, making the structural integrity of the vertical isolation grid paramount for maintaining quantum efficiency and minimizing crosstalk . The seal layer etch must completely clear the trench bottom while avoiding micro-masking from fluorocarbon polymers, a mechanism that becomes increasingly problematic as the trench aspect ratio increases and reactant transport becomes Knudsen-flow limited at smaller geometries . Real-time, physics-based control of the plasma state variables is often necessary to decouple the interdependent ion and chemical fluxes, ensuring robust repeatability across the wafer .
Risks & Challenges
[High] Etch Stop (Polymer Over-deposition): Excessive CFx polymer formation outpaces the physical removal rate driven by ion bombardment, completely halting the SiO2 etch process . This failure mode is highly sensitive to the source/bias power ratio and minor drifts in the process gas flow dynamics .
[High] Loss of Selectivity to Underlying Substrate: Insufficient polymer passivation on the exposed Si or SiN layer at the trench bottom allows fluorine radicals to aggressively attack the active substrate . This often occurs if reactor wall temperatures drift lower, increasing the wall's adsorption of polymerizing species and starving the wafer surface of protective fluorocarbons .
[Medium] Sidewall Roughness and Profile Bowing: Inadequate sidewall passivation or highly divergent ion bombardment causes lateral chemical etching, resulting in rough or bowed trench profiles . Similar to the artifacts seen in periodic Bosch processes, these geometric irregularities create localized stress concentrators that can cause the subsequent barrier and dielectric layers to crack under thermo-mechanical stress .
[Medium] Reactive Ion Micro-Trenching: Energetic ions deflect off the sloped or vertical polymer-coated sidewalls, concentrating the ion flux at the bottom corners of the trench . This localized enhancement of physical sputtering accelerates the etch rate specifically at the corners, creating deep micro-trenches that can penetrate the stopping layer and compromise underlying junction integrity .