The NMOS VT Adjust IIP (Ion Implantation) step immediately follows the lithography process that defines and exposes only the NMOS active regions P2. The primary objective of this step is to precisely calibrate the threshold voltage ($V_{TH}$) of the NMOS transistors by introducing a controlled dose of p-type dopants into the channel region T1. As demonstrated in P5, this threshold adjustment implant is purposefully executed through a sacrificial oxide layer rather than the final gate dielectric.