The NMOS Lightly Doped Drain (LDD) Ion Implantation (IIP) step is strategically positioned immediately after gate patterning and prior to sidewall spacer (SWS) deposition P3.By utilizing the patterned gate stack as a self-aligned hard mask, this process introduces n-type dopants precisely at the gate edges to form shallow junction extensions T3.As device geometries scale down, the drain electric field increasingly penetrates the channel region, compromising gate control and exacerbating short-ch