This process step performs the photolithographic patterning required to selectively expose the NMOS active regions while protecting the PMOS regions P2.By creating a patterned photoresist barrier, it prepares the wafer for the subsequent NMOS threshold voltage (Vth) adjustment ion implantation P4.Unlike the subsequent NMOS VT Adjust IIP step, which physically introduces the dopants into the silicon lattice P1, this photo step is strictly responsible for the spatial definition of the implant (Eng