HF breaks Si-O bonds to dissolve the oxide layer, exposing a hydrophobic silicon surface that prevents contamination during subsequent implant steps .
After the NMOS threshold voltage (VT) adjust ion implantation and the subsequent photoresist ashing and cleaning, the thin implant screen oxide mu
st be removed . This oxide was originally placed over the channel region to randomize the incoming ion trajectories, prevent channeling effects, and protect the bare silicon surface from metallic and organic contamination during the implant process . Because the high-energy ion bombardment physically damages the oxide network and embeds contaminants, leaving it in place would severely degrade the quality of the final gate dielectric . Therefore, a complete chemical removal of this compromised layer is required to expose a pristine silicon surface before growing the sacrificial oxide (SACOX) (Engineering Practice). Unlike a thick oxide hard mask removal, which requires aggressive etching to remove a structural blocking layer , this step targets a very thin, damaged screen oxide where minimizing substrate silicon loss and preventing isolation structure degradation are the primary concerns (Engineering Practice). The removal process relies on the chemical reaction between hydrofluoric acid (HF) and silicon dioxide . The HF effectively breaks the strong Si-O bonds, forming water-soluble complex ions that are easily rinsed away . Interestingly, the etch rate of this implant oxide is heavily influenced by the preceding ion implantation step; the physical collisions of the implanted dopants break local Si-O-Si bonds and introduce structural defects, rendering the oxide significantly more susceptible to chemical attack compared to unimplanted thermal oxide . This damage-enhanced etch rate means the oxide can be cleared very rapidly under controlled conditions (Engineering Practice). However, as the oxide clears, the bare silicon surface becomes exposed to the processing environment, rapidly transitioning from a hydrophilic oxide surface to a highly hydrophobic, hydrogen-terminated silicon surface . Dilute hydrofluoric acid (DHF) is universally selected for this step because it provides near-infinite selectivity to the underlying silicon substrate, ensuring that the critical channel silicon is not consumed . Although wet HF dipping is standard, careful control of dissolved oxygen in the bath is required to prevent concurrent re-oxidation and subsequent roughening of the fresh silicon surface . Alternatively, HF vapor cleaning can be employed to minimize dissolved oxygen issues, avoid water marks, and reduce metal contamination, ultimately producing an extremely smooth surface . The primary parameter interaction involves balancing the etchant concentration and exposure time: too short an exposure leaves residual damaged oxide and implant-induced contaminants, while excessive over-etching risks attacking the adjacent shallow trench isolation (STI) structures and causing unwanted topography . In a 40nm CMOS image sensor process, precise control of the NMOS threshold voltage is paramount for pixel readout and logic performance, necessitating exceptionally low defect densities at the surface . Because the subsequent steps involve growing and removing a sacrificial oxide to heal surface damage before the final thin gate oxide growth, any micromasking by residual implant oxide during this step will propagate roughness through the entire gate stack . Furthermore, the 40nm node's aggressive equivalent oxide thickness (EOT) targets leave zero tolerance for the mobility degradation that would result from a compromised initial silicon surface .
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