Ashing & Strip/Clean - 40nm

The hardened photoresist mask must be completely removed to enable deposition of the sidewall spacer pad oxide .

Following the NMOS LDD Ion Implantation, a hardened photoresist mask remains on the wafer and must be completely removed prior to the deposition of the sidewall spacer (SWS) pad oxide

. Unlike standard lithography steps, the photoresist here has been subjected to energetic dopant bombardment, transforming its upper layer into a highly cross-linked, carbonized crust known as High-Dose Ion-Implanted Photoresist (HDI-PR) . If this hardened mask and its associated organic or metallic residues are not thoroughly eliminated, subsequent dielectric depositions will suffer from poor adhesion and interface contamination, severely degrading device yield . This specific strip step is distinct from baseline cleans because it must aggressively dismantle the HDI-PR while preserving the ultra-shallow n-type dopant profiles introduced to mitigate short-channel effects . The removal of HDI-PR typically employs a synergistic combination of plasma ashing and subsequent wet chemical stripping . Traditional direct dry plasma ashing can induce severe plasma-induced damage (PID) to the gate dielectric, where collected charges create transient potential differences that drive damaging currents through the dielectric bulk and interface . To mitigate this, advanced processes may utilize plasma liquid-vapor activation (PLVA), where plasma introduces high-energy radicals and reactive oxygen/nitrogen species into a wet stripper without directly bombarding the wafer surface . These active species lower the apparent activation energy of the stripping reactions, promoting backbone scission and oxidation of the highly cross-linked PR polymer chains . By altering the surface hardness and elastic modulus of the crust, the activated wet chemistry can efficiently dissolve the HDI-PR without relying on purely physical, high-bias plasma sputtering that would otherwise risk substrate damage . Following the bulk removal of the photoresist, a rigorous wet clean is required to eliminate residual organic contaminants and metallic trace elements . A Sulfuric Peroxide Mixture (SPM), relying on strong oxidative reactions, is highly effective at decomposing persistent organic residues while exhibiting virtually zero etch rate on exposed silicon dioxide or high-k dielectrics . Conversely, ammonia-based mixtures (APM) must be carefully controlled or avoided here, as hydroxide ions can chemically etch exposed oxides and increase surface micro-roughness, which acts as a local electric field enhancement point that degrades device integrity . Process parameters such as plasma activation voltage in the ashing phase heavily dictate the concentration of active species; higher voltages initially increase the PR etch rate, but excessive potentials can lead to activity saturation or undesirable side reactions . At the 40nm node, the introduction of high-k/metal-gate architectures makes the structures exceptionally vulnerable to both thermal and plasma-induced degradation . Decreasing the physical thickness of the gate dielectric lowers the defect generation volume, but direct plasma exposure during resist stripping can still cause charge trapping that shifts the effective work function and threshold voltage . Therefore, balancing the high chemical reactivity needed to strip the LDD HDI-PR against the necessity of minimizing plasma exposure and substrate silicon loss is the fundamental engineering challenge of this specific step .

[High] Plasma-Induced Damage (PID) to Gate Dielectric: During the ashing phase, localized charge accumulation acts similarly to an antenna effect, establishing a potential difference across the high-k dielectric that drives a damaging current . This current breaks chemical bonds within the dielectric, creating oxygen vacancies and interface traps that subsequently degrade the threshold voltage stability and breakdown voltage of the device .
[High] Incomplete HDI-PR Crust Removal: Because the preceding LDD implant heavily cross-links the photoresist polymer chains, the surface hardness and elastic modulus of the resist are significantly altered . If the active radical concentration or chemical activation energy is insufficient during stripping, unremoved carbonized crust residues will block the subsequent SWS pad oxide deposition, leading to localized mask defects and integration failures .
[Medium] Substrate Surface Roughening: If APM-based wet chemistries are used excessively during the post-ash clean, the hydroxide ions will chemically attack the exposed silicon and field oxides . This chemical etching induces micro-roughness at the silicon surface, which can generate local electric field enhancement points that degrade carrier mobility and increase leakage currents in the underlying shallow junctions .
[Medium] Threshold Voltage Drift via EWF Shift: Exposure of high-k/metal-gate stack edges to oxidizing plasma conditions during ashing can alter the stoichiometry and interface dipoles of the effective work function (eWF) metals . This plasma-induced defect generation and charge trapping directly degrades the threshold voltage tunability, resulting in unacceptable parameter variation across the CMOS array .

The hardened photoresist mask must be completely removed to enable deposition of the sidewall spacer pad oxide .

Following the NMOS LDD Ion Implantation, a hardened photoresist mask remains on the wafer and must be completely removed prior to the deposition of the sidewall spacer (SWS) pad oxide

[High] Plasma-Induced Damage (PID) to Gate Dielectric: During the ashing phase, localized charge accumulation acts similarly to an antenna effect, establishing a potential difference across the high-k dielectric that drives a damaging current . This current breaks chemical bonds within the dielectric, creating oxygen vacancies and interface traps that subsequently degrade the threshold voltage stability and breakdown voltage of the device .
[High] Incomplete HDI-PR Crust Removal: Because the preceding LDD implant heavily cross-links the photoresist polymer chains, the surface hardness and elastic modulus of the resist are significantly altered . If the active radical concentration or chemical activation energy is insufficient during stripping, unremoved carbonized crust residues will block the subsequent SWS pad oxide deposition, leading to localized mask defects and integration failures .
[Medium] Substrate Surface Roughening: If APM-based wet chemistries are used excessively during the post-ash clean, the hydroxide ions will chemically attack the exposed silicon and field oxides . This chemical etching induces micro-roughness at the silicon surface, which can generate local electric field enhancement points that degrade carrier mobility and increase leakage currents in the underlying shallow junctions .
[Medium] Threshold Voltage Drift via EWF Shift: Exposure of high-k/metal-gate stack edges to oxidizing plasma conditions during ashing can alter the stoichiometry and interface dipoles of the effective work function (eWF) metals . This plasma-induced defect generation and charge trapping directly degrades the threshold voltage tunability, resulting in unacceptable parameter variation across the CMOS array .

40nm BSI CMOS Image SensorPreview

Process Cross-Section

Step highlight

In depth

Risks & Challenges

40nm BSI CMOS Image SensorPreview

Process Cross-Section

Step highlight

In depth

Risks & Challenges