40nm BSI CMOS Image SensorPreview

d transistor spacer structure [T2]. Positioned immediately after the lightly doped drain (LDD) implantation and subsequent resist stripping, this step prepares the wafer for the main SWS silicon nitride deposition [P4]. The primary integration logic for inserting a pad oxide before the main nitride spacer is two-fold: it protects the underlying crystalline silicon and gate dielectric edge from plasma damage during the subsequent anisotropic nitride etch, and it prevents the nitride layer from directly contacting the silicon substrate [P3]. Direct contact between high-stress silicon nitride and the silicon substrate would generate severe extended defects, altering carrier mobility and degrading junction leakage, following the film stress mechanisms described by the Stoney equation [P1]. The deposition process typically employs a chemical vapor deposition (CVD) or atomic layer deposition (ALD) method to form a highly conformal silicon dioxide layer [P3]. During deposition, precursor gases react at the heated wafer surface to form SiO2, a process driven by thermally activated surface kinetics [P3]. Because the underlying gate electrode presents a highly topographical step, achieving uniform film thickness on both vertical sidewalls and horizontal active areas is essential to ensure consistent final spacer width [P1]. The resulting oxide layer possesses a relatively low Young's modulus compared to the subsequent silicon nitride, allowing it to act as a mechanical compliance layer [P1]. By acting as a cushion, the intrinsic and thermal mismatch stresses of the overlying nitride layer are absorbed and redistributed by this pad oxide, thereby preventing stress-induced dislocations in the underlying silicon lattice [P1]. Silicon dioxide is selected as the pad material because it provides excellent etch selectivity relative to silicon nitride during the downstream reactive ion etching (RIE) step [P3]. This selectivity ensures that the anisotropic etch clears the nitride from planar surfaces without punching through the oxide into the underlying source/drain regions, an interaction principle essential for preserving substrate integrity [A1]. Furthermore, SiO2 naturally establishes a low interface state density with the silicon substrate, which is crucial for preventing interface-trap-assisted leakage at the junction edges, consistent with the interfacial layer behavior observed in dual-dielectric stacks [P2]. Process temperature during this deposition is kept strictly constrained; exceeding the thermal budget would cause undesirable lateral diffusion of the previously implanted LDD dopants, worsening short-channel effects such as threshold voltage roll-off and drain-induced barrier lowering (DIBL) [P4]. Consequently, low-temperature techniques like plasma-enhanced CVD (PECVD) or ALD are heavily favored to maintain the precise LDD profiles required for nanometer-scale devices while achieving the necessary conformality [P1]. In 40nm BSI (Backside Illuminated) CMOS Image Sensors, precise control of the SWS structure is critical because any junction leakage directly translates into dark current, severely degrading pixel performance [T1]. The highly conformal pad oxide ensures that the spacer width is extremely uniform across dense memory arrays, isolated logic, and pixel transistors, minimizing pattern density dependence across the chip [P1]. By keeping the parasitic source/drain resistance well-controlled and physically separating the deep source/drain implants from the channel edge, the resulting spacer structure maintains high drive current while suppressing off-state subthreshold leakage [T1].