40nm BSI CMOS Image SensorPreview

]. The preceding RIE plasma inevitably generates significant fluorocarbon polymeric residues and leaves metallic or organic contaminants on the exposed active areas [P4]. To successfully execute the subsequent NMOS Source/Drain and Floating Diffusion (FD) photolithography, the silicon surface must be restored to a pristine, implant-ready state [A1]. Unlike standard post-implant photoresist stripping, this particular step must eradicate hardened post-etch fluoropolymers and plasma-induced surface damage without causing additional silicon substrate recess [P2]. Preserving the structural integrity of the underlying silicon is critical, as any material loss directly degrades the electrical performance of the highly sensitive FD node [A1]. The process physically operates through a bipartite sequence combining gas-phase plasma ashing with highly selective wet chemical cleaning [A1]. Initially, an oxygen or forming gas plasma is deployed to physically bombard and chemically volatilize bulk organic residues, converting complex carbon species into exhaustible gases (Engineering Practice). Following the plasma ash, a targeted wet clean addresses the residual inorganic halide contaminants and non-stoichiometric damaged layers left by the dry etch [P3]. Typically, an ozone-rich deionized water rinse is utilized to vigorously oxidize residual carbon and metallic contaminants [P4]. Subsequently, a dilute acidic solution, such as hydrofluoric acid, selectively dissolves the newly formed sacrificial oxide and damaged silicon regions without aggressively attacking the underlying perfect crystal [P4]. This wet etching mechanism relies on a decoupled oxidation-dissolution cycle, ensuring that material removal is self-limiting and controlled at the sub-nanometer scale [P1]. The selection of cleaning chemistries is dictated by the absolute necessity for high selectivity between post-etch residues and the exposed silicon and silicon nitride structures [A3]. Dilute chemical combinations are preferred because they enable a kinetically controlled removal regime, where the reaction rate is governed by surface chemical kinetics rather than unpredictable hydrodynamic mass transport [P1]. If the selected wet cleaning chemistry possesses too high of an etch rate, it risks excessive consumption of the active silicon, leading to severe structural recess [P2]. Any significant silicon recess directly penalizes device performance by degrading the threshold voltage and increasing leakage currents [P2]. Furthermore, the solution must actively prevent localized surface roughening, since interface roughness violently degrades channel carrier mobility through enhanced surface scattering mechanisms [T1]. Therefore, formulation additives and process times are strictly modulated to guarantee complete residue dissolution while maintaining an atomically smooth semiconductor surface [A3]. In the context of nanoscale Backside Illumination (BSI) CMOS image sensors, the physical dimensions and leakage tolerances of the floating diffusion node are exceptionally stringent [A1]. Aggressive, single-step continuous etching or cleaning methods cannot meet the atomic-scale precision requirements of advanced CMOS limits [P1]. Instead, mild diffusion-controlled interface oxidation combined with selective wet etching is employed to gently reconstruct the interface and eliminate deep-level trap states [P3]. This meticulously controlled defect removal suppresses trap-assisted tunneling and thermal generation rates, which is fundamentally required to minimize the dark current in high-performance image pixels [T1].