40nm BSI CMOS Image SensorPreview

while selectively preserving it on the vertical gate sidewalls [A1]. In the process flow, this step immediately follows the deposition of a thin pad oxide and the bulk SWS nitride, and it prepares the device for the subsequent highly-doped Source/Drain (S/D) ion implantations [P3]. By dictating the exact physical separation between the gate edge and the deep S/D junctions, the spacer minimizes parasitic overlap capacitance and suppresses severe short-channel effects such as threshold voltage roll-off [T2]. Furthermore, the spacer acts as an essential buffer to reduce the peak electric field at the drain end, which directly mitigates hot-electron degradation in submicron MOSFETs [P3]. Unlike other generic nitride removal steps in the flow, such as hard mask etching or wet strip processes, this step relies entirely on geometric anisotropy rather than photolithographic patterning to define its final critical dimension (CD) [P1]. The core physical mechanism of this step relies on highly directional plasma etching to differentiate between horizontal and vertical surfaces [P1]. Traditional reactive ion etching leverages high-energy ion bombardment to physically sputter horizontal surfaces, but this can induce severe lattice damage and substrate recess [P1]. To overcome this in advanced nodes, the mechanism often employs a decoupled or cyclic "smart etch" strategy [P1]. In the first phase, a directional low-energy ion flux (such as H2 or He) is accelerated across the plasma sheath to selectively penetrate and break Si-N bonds solely on the horizontal surfaces, inducing chemical and structural modifications [P2]. Because the ions are highly directional, the vertical sidewalls remain largely unmodified [P1]. In the second phase, a chemically reactive neutral species (such as remote plasma NH3/NF3) selectively attacks the modified horizontal layer, forming volatile or sublimable salts like (NH4)2SiF6 [P1]. This two-step mechanism essentially decouples the anisotropic directionality from the chemical removal, enabling precise thickness control and nearly infinite selectivity to the unmodified vertical sidewalls and the underlying substrate [P1]. The selection of silicon nitride as the spacer material is driven by its excellent diffusion barrier properties and high dielectric constant, though its integration requires careful etch optimization to prevent unwanted device capacitance [P2]. The preceding thin pad oxide acts as a strain-relief buffer and a critical etch-stop layer to protect the underlying crystalline silicon from the energetic plasma [P2]. Process parameters must be precisely balanced; for instance, the RF bias voltage directly controls the ion energy, which in turn defines the penetration depth of the surface modification [P2]. Meanwhile, the neutral radical concentration governs the chemical reaction rate and the subsequent outgassing of the formed salts [P1]. If the ion energy is set too high, the anisotropic modification layer may extend too deep, leading to unwanted consumption of the vertical spacer CD and potential damage to the underlying pad oxide [P2]. For a 40nm BSI CMOS Image Sensor, precise spacer CD control is paramount because the variation in effective channel length directly impacts pixel drive current and noise performance [T1]. In front-side active areas of image sensors, the silicon substrate is exceptionally sensitive to plasma-induced defects; any over-etch that breaches the pad oxide and damages the silicon lattice will generate trap states [T3]. These traps act as generation-recombination centers that severely degrade sensor performance by increasing localized dark current (Engineering Practice). Therefore, the highly selective surface-state-dependent etching mechanism is essential at this node to ensure horizontal nitride clearing without compromising the integrity of the underlying silicon substrate [P1].