The preceding step, NMOS VT Adjust IIP, utilizes a patterned photoresist mask to block p-type dopants from entering non-NMOS regions while allowing implants through a sacrificial oxide in the target active areas T1.After the implant modifies the local carrier concentration to set the NMOS threshold voltage, the highly cross-linked photoresist mask must be completely removed before proceeding to high-temperature thermal steps P3.If left on the wafer, the carbon-rich resist would undergo severe ca