40nm BSI CMOS Image SensorPreview

ock p-type dopants from entering non-NMOS regions while allowing implants through a sacrificial oxide in the target active areas [T1]. After the implant modifies the local carrier concentration to set the NMOS threshold voltage, the highly cross-linked photoresist mask must be completely removed before proceeding to high-temperature thermal steps [P3]. If left on the wafer, the carbon-rich resist would undergo severe carbonization during subsequent oxidations, degrading the crystalline device structure [P1]. Therefore, this specific Ashing & Strip/Clean step serves to eradicate the implant-hardened photoresist and any organic or metallic contaminants prior to the Implant Oxide Removal step [P1]. This ensures that the subsequent Sacrificial Oxidation and final gate dielectric growth occur on a pristine silicon surface, preventing defect incorporation [P2]. The physical mechanism of photoresist removal is typically a two-stage process combining dry plasma ashing and wet chemical cleaning [P1]. During the dry ashing phase, an O2-based plasma generates highly reactive oxygen radicals that oxidize the organic polymers into volatile byproducts such as CO and CO2 [P1]. However, because the upstream high-energy ion implantation breaks polymer bonds and depletes hydrogen, a hardened, carbonized "crust" forms on the outer surface of the resist (Engineering Practice). Standard O2 plasma alone often struggles to penetrate this crust without excessively high thermal budgets, necessitating a follow-up wet clean (Engineering Practice). The wet cleaning phase heavily relies on strongly oxidative mixtures, such as the Sulfuric Peroxide Mixture (SPM), which effectively decomposes remaining complex organic contaminants via powerful oxidative reactions [P2]. Crucially, SPM removes these organics while virtually not etching the underlying sacrificial SiO2 layer, preserving the structural integrity of the active area surface [P2]. The selection of SPM over alkaline-based cleans like APM (Ammonia Peroxide Mixture) at this specific juncture is driven by the strict requirement to protect the underlying sacrificial oxide from premature etching and to avoid introducing surface micro-roughness [P2]. APM contains OH- ions that can chemically etch SiO2, potentially creating local electric field enhancement points that degrade the dielectric reliability of the future gate oxide [P2]. Furthermore, prolonged plasma exposure during the ashing phase can introduce trap states and damage underlying dielectric structures, which has been shown to shift effective work functions and degrade threshold voltage tunability in advanced CMOS integrations [P3]. Thus, the ashing parameters must be carefully balanced to penetrate the implant-hardened resist crust without inducing deep plasma damage or causing unintentional thermal diffusion of the newly implanted dopants in the NMOS channel [A1]. At the 40nm node, precise threshold voltage control is paramount because short-channel effects and threshold roll-off become exponentially more pronounced as dimensions shrink [T1]. Any residual organic contamination or metallic impurities driven into the silicon during the subsequent Implant Oxide Removal and Sacrificial Oxidation steps would critically degrade carrier mobility and gate oxide integrity [P2]. Consequently, this cleaning sequence must be highly selective and entirely residue-free, ensuring the delicate threshold voltage calibration—governed by the flat-band voltage and depletion region charge established in the previous IIP step—remains perfectly intact [T1].