In 40nm BSI CMOS Image Sensor manufacturing, the wafer is inverted and bonded to a carrier so that backside interconnects and contacts can be formed A2.After sequentially etching through the backside dielectric layers, including the BPMD and the high-k/anti-reflective (HKD/AR) stacks, this specific step etches into the bulk silicon substrate to form the localized backside contact trench A1.Unlike global substrate thinning or the SWS Nitride Anisotropic Back Etch which targets specific dielectric