Following the CIS/ISP Wafer TC Bond and subsequent anneal, the stacked structure consists of two full-thickness silicon wafers physically integrated together A2.To construct a Back-Side Illuminated (BSI) CMOS Image Sensor, the original silicon bulk of the CIS wafer must be radically thinned to expose the photoactive regions to incoming light P3.The CIS Backside Wafer Surface Grind step performs the initial bulk material removal, acting as the coarse thinning phase before fine polishing P4.Withou