40nm BSI CMOS Image SensorPreview

Back-Side Illuminated (BSI) CMOS Image Sensor, the original silicon bulk of the CIS wafer must be radically thinned to expose the photoactive regions to incoming light [P3]. The CIS Backside Wafer Surface Grind step performs the initial bulk material removal, acting as the coarse thinning phase before fine polishing [P4]. Without this aggressive structural modification, incident photons would be completely absorbed in the thick, highly doped substrate before reaching the underlying Pinned Photodiodes (PPD) [P3]. Furthermore, this bulk grinding systematically removes the deep intrinsic gettering regions originally present in the starting silicon substrate [P1]. This step directly prepares the wafer for subsequent edge-grinding and chemical-mechanical planarization (CMP) by reducing the substrate to a manageable thickness while maintaining global planarity [P4]. Unlike the subsequent edge-grind which specifically profiles the wafer rim to prevent chipping, this surface grind operation targets the entire backside planar area to achieve rapid vertical thickness reduction [A3]. The surface grinding process fundamentally relies on mechanical abrasion driven by a rapidly rotating grinding wheel equipped with diamond or abrasive grit (Engineering Practice). The mechanism is purely mechanical, utilizing high shear and compressive stresses to physically fracture and remove the crystalline silicon bulk [P4]. As the abrasive particles engage the silicon surface under a controlled downforce, they propagate micro-cracks that coalesce, resulting in the continuous spallation of silicon material [P2]. The removal rate in such mechanical thinning operations is exceptionally high, making it capable of removing hundreds of micrometers of material very quickly [P4]. However, this violent mechanical action unavoidably introduces a subsurface damage layer characterized by severe work-hardening, dislocations, and micro-fractures in the remaining silicon crystal [A1]. This mechanically induced stress layer necessitates the subsequent CMP operations to chemically and mechanically remove the damaged zone and restore a pristine crystalline surface for light reception [A1]. Grinding is selected as the primary bulk thinning method because chemical wet etching or CMP alone would be prohibitively slow and expensive for removing the majority of a full-thickness wafer [P4]. To mitigate the immense shear forces and prevent wafer breakage during grinding, specialized protective adhesive films with engineered storage modulus gradients are often applied to the frontside (or the ISP side of the bonded pair) to buffer the stress and conform to any structural topographies [A3]. The process control relies on careful tuning of the wheel rotation speed, chuck rotation speed, and vertical feed rate (Engineering Practice). A higher vertical feed rate maximizes throughput but simultaneously increases the depth of the subsurface damage and degrades the Total Thickness Variation (TTV) across the wafer [A1]. Therefore, the grind is typically executed in two consecutive stages: a coarse grind with larger grit for rapid removal, followed by a fine grind with smaller grit to reduce the resultant surface roughness and minimize the damage layer depth (Engineering Practice). In advanced 40nm BSI-CIS nodes, the active epitaxial layer is extremely thin, which maximizes the optical acceptance angle and minimizes optical and carrier crosstalk between highly scaled pixels [P3]. Consequently, the total remaining silicon thickness after the entire thinning module is critically constrained, leaving almost zero margin for deep mechanical damage to penetrate the pixel active regions [A1]. Furthermore, because the bulk gettering sinks are entirely eliminated during this grinding step, the 40nm BSI architecture relies heavily on engineered proximity gettering—such as hydrocarbon molecular ion implantation—located near the epitaxial layer to capture metallic impurities like copper diffusing from the hybrid bond interface [P1].