CIS Backside Wafer Surface Grind - 40nm | SemiFlows

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CIS Backside Wafer Surface Grind

292CIS Backside Wafer Surface Grind 293CIS Backside Wafer Edge-Grind 294ultrasonic clean 295CIS Backside Si, CMP1 296CIS Backside Si, CMP2 (target thickness adjust)297ultrasonic cleaning

Process Cross-Section

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Step highlight

Backside surface grinding removes silicon across the wafer plane to reduce thickness while preserving edge integrity [A3].

In depth

Following the CIS/ISP Wafer TC Bond and subsequent anneal, the stacked structure consists of two full-thickness silicon wafers physically integrated together [A2]. To construct …

Related steps

CIS Backside Wafer Edge-Grind
ultrasonic clean
CIS Backside Si, CMP1
CIS Backside Si, CMP2 (target thickness adjust)
ultrasonic cleaning