40nm BSI CMOS Image SensorPreview

subsequent bulk backside surface grinding, the top CIS wafer is drastically thinned while the bottom ISP wafer remains thick (Engineering Practice). Because surface grinding removes bulk material uniformly across the top surface without altering the wafer's circular perimeter, it inherently leaves a razor-sharp, fragile "knife-edge" at the periphery of the thinned wafer [A2]. Furthermore, the extreme periphery of bonded wafer pairs often contains an unbonded region due to edge roll-off from prior polishing steps [A2]. If left untreated, this sharp, weakly bonded edge would fracture during the turbulent fluid dynamics of the upcoming ultrasonic clean or catch on the polishing pad during the subsequent CMP steps, causing severe peeling and particle contamination [A1]. Therefore, the CIS Backside Wafer Edge-Grind step is strictly required to reshape the wafer perimeter, structurally stabilizing the bonded pair for downstream processing [A2]. The edge-grind process relies on mechanical abrasion using a specifically profiled diamond grinding wheel to remove the fragile overhanging silicon and contour the wafer edge into a tapered or convex shape [A2]. Unlike surface grinding, which applies uniform planar pressure to remove bulk thickness, edge grinding selectively addresses the localized stress concentration at the bonded perimeter [A2]. By physically removing the unbonded peripheral region, the process eliminates micro-cracks and bonding defects that naturally occur at the wafer edge during the preceding hybrid bonding step [P4]. The mechanism of material removal involves brittle fracture of the silicon crystal lattice under the localized shear stress of the abrasives, which inherently leaves a thin work-hardened or micro-damaged surface layer [A1]. This edge reshaping reduces the macroscopic stress concentration at the interface, helping to mitigate the severe thermo-mechanical bow and warp phenomena common in highly stressed, thinned silicon substrates [P2]. A precision-contoured abrasive wheel is selected to match the desired bevel angle and depth, ensuring that the grinding removes only the unbonded edge without encroaching into the active pixel array (Engineering Practice). The process parameters, such as wheel rotation speed, feed rate, and coolant flow, must be carefully balanced to prevent excessive localized heating and subsequent thermal stress propagation [P2]. If the feed rate is too high, the mechanical shear forces can induce deep crystal dislocations or initiate lateral crack propagation along the bonding interface [P2]. Conversely, a highly optimized edge profile not only prevents mechanical failure but also enhances the optical recognition of the wafer edge for alignment sensors in subsequent photolithography or metrology equipment [A2]. The use of deionized water as a coolant during this step is critical to flush away the silicon swarf, preventing it from adhering to the freshly ground surface before the subsequent ultrasonic cleaning operation (Engineering Practice). For advanced 40nm BSI CMOS image sensors, the active epitaxial silicon layer must be severely thinned to optimize the optical path and carrier collection efficiency [P1]. At these extreme thinness levels, the ratio of inherent thin-film stress to substrate rigidity becomes highly unfavorable, making the wafer edge exceptionally susceptible to micro-cracking during handling [P2]. Therefore, achieving a perfectly controlled edge bevel is no longer a cosmetic requirement but a fundamental structural necessity to preserve the integrity of the ultra-thin CIS layer through final via and pad formation processes [P3].