40nm BSI CMOS Image SensorPreview

con handle must be drastically thinned to allow direct backside illumination, which maximizes the fill factor and light absorption efficiency [A1]. Following mechanical grinding and the primary CMP1 step, which removes severe mechanically induced subsurface damage, the CIS Backside Si CMP2 step acts as the final, highly precise target thickness adjustment [P3]. This secondary polishing step is critical for achieving a stringent Remaining Silicon Thickness (RST) and minimizing Total Thickness Variation (TTV) across the wafer [A1]. Uniform substrate height is absolutely essential for BSI sensors because the silicon thickness directly defines the optical absorption path length for incident photons [T2]. If the RST varies across the wafer, the optoelectronic conversion efficiency—particularly for longer-wavelength red light that penetrates deeper into the silicon crystal—will exhibit severe non-uniformity, degrading image quality [T2]. Furthermore, this step prepares the pristine, ultra-smooth surface required for the subsequent oxide hard mask deposition and backside lithography steps (Engineering Practice). The material removal mechanism during this CMP step relies on a microscale plastic removal process driven by the strict synergy of chemical softening and mechanical abrasion [P2]. In a specifically formulated alkaline slurry environment, chemical components react with the silicon surface to form a hydrated or passivated layer with significantly reduced mechanical properties, typically characterized as a lower dynamic hardness [P2]. Subsequently, nanoscale abrasive particles suspended in the slurry, supported by the polishing pad asperities, engage the wafer in sliding or rolling contact to gently shear away the softened layer [P2]. The overall removal rate is macroscopically governed by Preston's equation, which dictates a linear dependence on down pressure and the relative velocity between the pad and the wafer [P2]. To achieve the extreme precision required for CMP2, the process shifts focus from bulk removal to atomic-level surface smoothing, necessitating highly uniform load distribution across all active abrasives [P4]. Real-time control of this precise thinning is facilitated by in-situ optical spectral measurements, which analyze thin-film interference reflections to invert the current film thickness without interrupting the polishing process [A2]. The selection of specific slurry chemistries and abrasive morphologies for CMP2 is intentionally tailored to favor extraordinary surface quality over raw material removal rate [P3]. Colloidal silica slurries are typically selected because their continuous, mild hydration of the silicon surface prevents the direct mechanical fracturing that would otherwise inject new crystallographic defects [P4]. Additionally, tuning the abrasive particle size distribution—such as utilizing precisely engineered mixed abrasive slurries—can optimize the interface contact state, shifting the wear mechanism from unpredictable three-body rolling to highly efficient two-body sliding wear [P4]. This controlled abrasive interaction minimizes the ineffective frictional energy dissipation that causes micro-scratches [P4]. To combat cross-wafer non-uniformity and temporal pad wear effects, advanced pad conditioning techniques are employed to maintain consistent contact area and pressure uniformity throughout the run [P3]. Integrating an equivalent light source spectrum methodology for in-situ thickness measurement isolates the true wafer reflection from the complex optical interference of the intermediate slurry and pad layers, guaranteeing the target RST is achieved with nanometer precision [A2].