40nm BSI CMOS Image SensorPreview

strate to allow direct light incidence onto the photodiode region without interference from the frontside metal routing layers [T1]. Following bulk mechanical grinding and ultrasonic cleaning, the wafer surface exhibits significant sub-surface damage, work-hardened zones, and topographical variations, known as total thickness variation (TTV) [A2]. The CIS Backside Si, CMP1 step is a high-removal-rate planarization process designed to rapidly strip away this structurally compromised silicon layer [P1]. By doing so, it acts as an intermediate transition, preparing a relatively smooth, damage-free, and uniform silicon surface for the subsequent highly precise CMP2 target thickness adjustment [P3]. The core mechanism of silicon CMP relies on the dynamic synergy of chemical surface softening and mechanical shear [P1]. Under an alkaline environment, chemical additives in the slurry rapidly oxidize and hydrate the exposed silicon surface, forming a passivating reaction layer with significantly reduced mechanical strength [P2]. Nanoscale silica abrasives, suspended in the slurry and pressed against the wafer by the polishing pad, engage the softened layer through sliding and indentation contacts [P4]. The material removal occurs as these active abrasives plastically plow and shear off the chemically modified surface, while the bulk crystal underneath remains undisturbed [P4]. The overall removal rate follows Preston's law, where the material removal is proportional to the applied down-pressure and the relative sliding velocity between the pad and the wafer [P2]. The slurry formulation specifically incorporates removal-rate enhancers, such as alkanolamines, which promote rapid silicon hydration and chemical softening [A1]. To prevent the formation of insoluble polishing debris that could clog the pad, basic amino acids are co-introduced to regulate and stabilize the interfacial reaction products via complexation [A1]. A silica-based abrasive is selected because its hardness is properly matched to the hydrated silicon layer, ensuring efficient removal without inducing deep mechanical scratching [A1]. Furthermore, the choice of polishing pad directly influences the mechanical contact stress distribution and slurry fluid dynamics; structured pads are utilized to ensure uniform slurry transport and prevent localized pressure concentrations that exacerbate wafer non-uniformity [P3]. In a 40nm BSI architecture, controlling the precise distance between the backside surface and the built-in active pixel regions is critical for quantum efficiency and optical crosstalk mitigation [T1]. Because the remaining silicon membrane is extremely thin, any residual stress or micro-cracking from the grinding phase can propagate and degrade the dark current performance of the photodiodes [A2]. Therefore, the CMP1 step must carefully balance a high chemical removal component against mechanical downforce to minimize the introduction of new defects [P1]. The precise tuning of slurry pH and the concentration of chemical enhancers ensure that the process window strictly favors chemical softening, thereby arresting any mechanically induced lattice damage before the final polishing step [A1].