40nm BSI CMOS Image SensorPreview

trical stabilization phase following the initial room-temperature thermocompression bonding of the CMOS Image Sensor (CIS) and Image Signal Processor (ISP) wafers [A3]. During initial contact, the hybrid wafer interface relies primarily on weak van der Waals forces and hydrogen bonding [P4]. Because the subsequent process flow requires aggressive mechanical bulk silicon removal, such as backside surface grinding, the bonding interface must be significantly strengthened to prevent macroscopic delamination [P4, A3]. The thermal anneal provides the activation energy necessary to convert these weak initial attractions into robust covalent bonds across the dielectric regions, while simultaneously enabling metal-to-metal fusion at the interconnect pads to finalize the direct bond interconnects (DBI) [A2]. The physical mechanism of dielectric bonding centers on dehydration condensation and interfacial atomic rearrangement [P3]. Interfacial hydroxyl (–OH) groups, which terminate the surfaces following pre-bond activation and cleaning, react under elevated temperatures to form stable siloxane (Si–O–Si) covalent bonds while releasing water as a byproduct [P3]. If advanced oxynitride dielectric layers are utilized, the high-density dangling bonds generated by plasma exposure undergo chemical bond rearrangement during the anneal, establishing a highly stable, covalent transition layer [A1]. Concurrently, the thermal energy drives solid-state diffusion and atomic-scale reconstruction at the copper-to-copper (Cu–Cu) interfaces [P4]. The elevated temperature induces thermal expansion of the Cu pads, bringing opposing surfaces into intimate contact and driving atomic diffusion across the boundary to eliminate microscopic gaps and residual oxides, thereby ensuring optimal electrical connectivity [P1, P4]. The selection of anneal temperature and duration is strictly governed by a fundamental trade-off between interfacial bond strength and the thermal budget limitations of the active semiconductor devices [P4]. Conventional high-temperature thermal treatments can induce unwanted dopant diffusion, which degrades the abruptness of shallow junctions and increases transistor off-current, negatively impacting sensor performance [P2]. Furthermore, excessive temperatures can trigger the outgassing of hydrogen or volatile byproducts from non-equilibrium films like PECVD oxide, leading to pressure build-up and void formation at the interface [P3]. Therefore, the process is engineered to operate at moderate temperatures (typically 250 °C to 350 °C), relying on prior surface activation to lower the required activation energy for bonding, while utilizing extended soak times to allow interfacial water molecules to diffuse out completely [P1, P3]. For nanoscale Backside Illuminated (BSI) CMOS image sensors, the hybrid bonding pitch typically scales to sub-micrometre-scale dimensions, elevating the physical demands on the thermal cycle [P1]. At these extreme interconnect densities, the total volume of Cu is highly constrained, reducing the available thermal expansion required to close the post-CMP recesses [P1]. Consequently, the anneal process must be meticulously tuned in conjunction with the dielectric material properties (such as SiCN) to ensure that the required Cu–Cu physical contact is achieved without exerting excessive thermomechanical stress, which could fracture the surrounding inter-metal dielectric or cause Cu migration failures [P1].