40nm BSI CMOS Image SensorPreview

ck-Illuminated CMOS Image Sensor (BI-CIS) wafer is logically and physically staged with a corresponding Image Signal Processor (ISP) wafer [P1]. Following the final oxide chemical-mechanical planarization (CMP) and post-CMP cleaning, the wafers present highly planarized hybrid surfaces consisting of copper pads embedded in a dielectric matrix [P1, T3]. This pairing step strictly precedes surface activation and optical alignment, ensuring that the appropriate known-good dies or matching functional yield maps on both wafers are correlated before committing them to the irreversible hybrid bonding sequence [P1]. Unlike the subsequent alignment step that physically registers fiducials, or the thermal-compression (TC) bond step that establishes physical mating, this step functions to establish the designated wafer pair, verify the compatibility of incoming CMP topographies, and synchronize their loading into the bonding cluster [P1]. The underlying necessity for meticulous pairing stems from the stringent physical requirements of Cu-Cu hybrid bonding, which relies on simultaneous metal-to-metal atomic diffusion and dielectric-to-dielectric chemical bonding [P1]. Because the ultimate bonding mechanism depends on initial van der Waals adhesion followed by covalent bond formation across the interface, any macroscopic mismatch in wafer bow, warp, or global topography can inhibit the necessary intimate contact [P1, P2]. By evaluating the CMP-induced copper recess, dishing, and dielectric erosion profiles of both the CIS and ISP wafers during this pairing phase, the process ensures that the combined topographical variations fall within the strict tolerance limits required to prevent interface gaps [P2]. This carefully prepares the selected pair for the subsequent RF plasma or surface-activated bonding (SAB) steps, which require pristine, proximate surfaces to allow high-density dangling bonds to interact and fuse effectively [P3, A1]. The strategic implementation of a pre-activation pairing module also serves to mitigate the risk of time-dependent surface degradation [P3]. Hybrid bonding surfaces, particularly the exposed copper interconnects, are highly susceptible to spontaneous oxidation and airborne organic contamination, both of which act as severe barriers to the low-temperature atomic-scale reconstruction needed for high-quality junctions [P3]. By pairing the wafers into a unified carrier or load port immediately prior to in-situ RF surface activation, the queue time is strictly minimized and synchronized, preserving the high surface energy states generated during subsequent activation [P3]. Furthermore, this logistical pairing supports the advanced integration of heterogeneous layers, such as oxynitride bonding films or low-k dielectrics, which depend on carefully matched geometric designs and surface energies to achieve robust direct bonding at the reduced thermal budgets required by temperature-sensitive image sensors [T3, A1].