The CIS/ISP wafer bond pairing step is the critical integration juncture in the packaging module where a fully processed Back-Illuminated CMOS Image Sensor (BI-CIS) wafer is logically and physically staged with a corresponding Image Signal Processor (ISP) wafer P1.Following the final oxide chemical-mechanical planarization (CMP) and post-CMP cleaning, the wafers present highly planarized hybrid surfaces consisting of copper pads embedded in a dielectric matrix P1, T3.This pairing step strictly p