40nm BSI CMOS Image SensorPreview

and dielectric layers (Engineering Practice). Unlike Optical Pad 3 Etch which tackles the uppermost organic or planarization films, and Optical Pad 1 Etch which clears the final barrier immediately above the metal, Optical Pad 2 Etch is specifically positioned to remove the bulk intermediate dielectrics (typically thick SiO2 or SiN) while maintaining strict profile control [P2]. It follows the Lower OCL Etch, ensuring that the optical planarization structure is defined before bulk dielectric removal in the pad region begins [A2]. This multi-step partitioning prevents catastrophic mask erosion and minimizes charge-induced damage to the final metal pad by keeping a protective dielectric layer intact until the final Pad 1 and Grid Seal etches [P2]. The core mechanism of this step relies on Inductively Coupled Plasma Reactive Ion Etching (ICP-RIE) utilizing a fluorocarbon-based chemistry, consistent with high-density plasma etch principles [P1]. The plasma generates reactive fluorine radicals and energetic ions that break the Si-O or Si-N bonds to form volatile byproducts such as SiF4 [P1]. Simultaneously, the fluorocarbon precursors form a carbon-rich polymer layer on the sidewalls, which passivates the surface and minimizes lateral etching, thereby ensuring a highly anisotropic profile [P1]. The physical ion bombardment provides the necessary directional energy to clear the polymer from the trench bottom, allowing the chemical etch to proceed vertically into the substrate [P3]. For intermediate layers containing silicon nitride, low-temperature fluorination mechanisms can also be leveraged, where cyclic interactions between fluorine precursors and inert plasma bombardment selectively remove the material without inducing severe thermal stress [A1]. Fluorocarbon gases (such as CF4, C2F6, or CHF3) mixed with polymerizing agents (like CH4 or H2) are selected to precisely tune the Carbon-to-Fluorine (C/F) ratio in the plasma [P1]. This ratio dictates the fundamental competition between the active etching of the dielectric and the deposition of the protective polymer, a balance critical for achieving deep etching without micro-trenching or profile bowing [P1]. Adjusting the residence time of these gases in the chamber controls radical dissociation and significantly impacts both the etch selectivity and the overall removal rate [P1]. Furthermore, ICP power is utilized to control the plasma density and chemical radical generation, while bias power dictates the ion bombardment energy [P3]. These parameters must be carefully co-optimized to prevent physical sputtering damage to the surrounding pixel arrays, similar to how etch-stop layers protect underlying structures during high-speed etching [P2]. In 40nm technology, the aspect ratio of the bond pad vias becomes more aggressive due to the scaling of device footprints and the necessity of thick optical stacks required to maximize photon capture efficiency [P4]. As device dimensions shrink, maintaining low parasitic capacitance and resistance at the pad interfaces is vital for high-speed readout, adhering to the physical limits of RC delay outlined in scaling theories [T2]. The transition through multiple sequential pad etches (Pad 3, 2, 1) mitigates the risk of localized charging effects (arcing) that are exacerbated in scaled nanometer nodes [A1]. This stepwise approach guarantees that the intricate topology of the nanoscale optical layers is preserved while providing reliable, low-resistance electrical access to the underlying circuitry [P4].