40nm BSI CMOS Image SensorPreview

ractice)*. The process sequence—Si Etch followed by Pad Oxide Etch, then CESL (Contact Etch Stop Layer) and PMD (Pre-Metal Dielectric) etches—indicates a reverse-order deconstruction of the structural layers from the wafer's backside [P1]. Early front-end pad oxide etches (such as step #10) are used to prepare active areas by acting as a strain buffer beneath deposited silicon nitride [P2]. In contrast, this specific backend pad oxide etch serves to remove the interfacial oxide layer that is exposed only after the bulk silicon has been etched away [P1]. By completely clearing this specific pad oxide, the process exposes the underlying nitride-based CESL and oxide-based PMD layers, preparing the structural pathway for subsequent etches to finally reach the metal pad [P1]. The removal of the oxide layer typically relies on fluorocarbon-based reactive ion etching (RIE) to achieve directional removal [P1]. The fundamental mechanism combines plasma chemical reactions, where fluorine radicals form volatile byproducts, with momentum transfer from normal-incidence accelerated ions [P1]. During inductively coupled fluorocarbon plasma etching, the balance between material removal and polymer deposition dictates the selectivity of the etch [P3]. Fluorocarbon species continuously form a protective polymer layer on the exposed substrate surfaces [P3]. However, SiO2 etching is driven by ion-assisted chemical reactions that easily penetrate and consume this oxygen-rich polymer layer, allowing the oxide etch rate to remain high and relatively constant [P3]. Inductively coupled plasma (ICP) or similar high-density RIE platforms are selected for this step because they decouple plasma generation from ion biasing, allowing for fine-tuned control over ion bombardment energy [P4]. To maximize the etch efficiency of the pad oxide while preventing premature consumption of the underlying CESL nitride, reactor wall conditions must be carefully managed [P3]. Elevated reactor wall temperatures reduce the loss of fluorocarbon species to the chamber walls, which in turn redistributes these radicals to form thicker passivating polymer films on the cooler wafer surface [P3]. This polymer strongly suppresses the etching of non-oxygen-containing materials (like the subsequent SiN layer), thereby enhancing the selectivity of the oxide etch over adjacent interfaces [P3]. While wet etch approaches using high concentrations of HF can also fully remove pad oxides to expose underlying sidewalls without plasma damage [A1], dry RIE is strictly preferred in deep bond pad openings to maintain vertical, highly anisotropic profiles (Engineering Practice). At the 40nm node, advanced constant-field scaling dictates that dielectric layers are proportionally thinner, making strict interface control critical to prevent field-enhancement issues and parasitic leakages [T2]. The transition to highly scaled structures means that any uncontrolled lateral etching or profile micro-loading can severely impact integration [T2]. Therefore, the pad oxide etch must be strictly anisotropic to maintain straight profiles without foot formation at the base of the opening [P4]. This precision ensures that the subsequent CESL and PMD etches are perfectly aligned to the metal pad target, preventing electrical shorts or mechanically weak bond pad formations (Engineering Practice).