40nm BSI CMOS Image SensorPreview

ght enters from the backside, necessitating the thinning of the silicon substrate (Engineering Practice). To connect the sensor to external circuitry, bond pads located in the front-side metallization must be accessed from the backside [P1]. Following backside silicon thinning and initial surface treatments, this specific lithography step, Bond Pad Opening 3 - Photo, defines the mask for the deep backside via trench [A1]. Unlike earlier intermediate cavity formations, this step precisely defines the boundary for the subsequent sequential removal of the remaining silicon, the underlying isolation pad oxide, and the contact etch stop layer (CESL) to ultimately expose the front-side landing pad [A1]. This backside via approach significantly shortens the interconnect length for heterogeneous process system integration, as demonstrated in 3D through-chip interconnect architectures [P3]. The photolithography process relies on the precise projection of UV light through a reticle to chemically alter the solubility of the photoresist [A1]. For deep backside openings, a thick photoresist layer is required to withstand the prolonged subsequent anisotropic silicon etching [P3]. The lithographic resolution and overlay accuracy are critical here, as misalignment can lead to missing the front-side landing pads, which severely degrades interconnect yield [P3]. To compensate for systematic variations such as optical distortion from neighboring layout patterns, elaborate mathematical optical proximity correction (OPC) is applied to the reticle design [T1]. Furthermore, managing the profile of the developed resist is essential because the subsequent plasma etch will transfer this profile into the deep silicon trench, and any mask erosion can cause undesirable via tapering [P4]. The selection of a thick, high-viscosity photoresist is driven by the need for high etch selectivity during the deep Si Etch and subsequent dielectric etches (Engineering Practice). The photoresist must maintain structural integrity and adhesion to the backside dielectric during the high-energy ion bombardment of the plasma etching steps [A1]. The soft-bake and hard-bake temperature parameters are strictly controlled to optimize the resist's cross-linking density without inducing excessive thermal stress that could cause resist cracking or delamination from the substrate [A2]. Additionally, the exposure dose and focus offset parameters are tuned to achieve vertical sidewalls in the thick resist, ensuring the final exposed contact area meets the requirements for low spreading resistance and reliable ohmic contacts, which scale inversely with the contact area [T2]. At the 40nm node for BSI CIS, the pixel pitch is highly scaled, leaving very limited real estate for peripheral bond pads and requiring tight overlay control between the backside lithography and the front-side metal features [P1]. The high density of these interconnects demands minimizing pad sizes, which in turn requires exceptional alignment capability during the photo step to prevent copper diffusion or migration issues if the via misses the barrier layer [P2]. Furthermore, exposing the active circuitry to mechanical stresses during subsequent packaging requires careful pad layout, such as Bond Over Active (BOA) designs, to dissipate stress away from the fragile low-k dielectrics used in advanced nodes [P1].