40nm BSI CMOS Image SensorPreview

pad or through-silicon via (TSV) landing pad from the backside requires etching through a highly complex, thick stack of dielectric materials [A1]. Following the sequential opening of the Pad Oxide and Contact Etch Stop Layers (CESL 1 and 2), the PMD 1 Etch initiates the bulk removal of the Pre-Metal Dielectric (PMD) stack [P1]. Because the total dielectric thickness in BSI architectures is substantial, the complete etch sequence is divided into multiple stages (PMD 1 through 4) to maintain strict profile control and manage thermal budgets [A2]. This initial bulk etching step prepares the via profile for subsequent PMD etches, ultimately enabling vertical low-resistance interconnects that minimize IR drop and parasitic inductance in the power or signal delivery paths [A1]. The PMD 1 Etch primarily relies on reactive ion etching (RIE) utilizing fluorocarbon-based plasmas to selectively remove the SiO2-based dielectric [P1]. The fundamental mechanism is driven by ion-chemical synergistic reactions, where directional ion bombardment breaks surface chemical bonds while neutral fluorine radicals form volatile byproducts [P1]. As the etch progresses deeper into the PMD layer, the process is heavily influenced by aspect-ratio-dependent etching (ARDE) [P2]. This ARDE phenomenon occurs because the transport-limited delivery of neutral reactants decreases at the bottom of high depth-to-width structures due to geometric shadowing [P2]. To counteract lateral etching and maintain vertical sidewalls, fluorocarbon polymers naturally generated by the plasma deposit on the sidewalls as a protective passivation layer, mimicking the passivation mechanisms widely utilized in high-aspect-ratio anisotropic etching [P3]. Fluorocarbon chemistry is explicitly chosen for its high anisotropy and ability to maintain robust selectivity against underlying or adjacent metallic and polysilicon structures [P1]. The delicate balance between the vertical etch rate and sidewall roughness is dictated by the ratio of etching radicals to passivating polymer precursors [P3]. Radio-frequency (RF) bias power is a critical tuning parameter; higher RF power increases the kinetic energy of bombarding ions, which enhances the vertical etch rate but can induce physical damage to the etched surface or severely degrade mask selectivity [P1]. Furthermore, managing the substrate temperature during the etch is essential, as elevated temperatures can reduce the stability of the etch-inhibiting polymer layer, shifting the process from a surface-reaction-controlled regime to a neutral-transport-limited regime [P2]. At the 40nm technology node, stringent design rules dictate precise critical dimension (CD) control during deep via and pad openings [P2]. The extreme integration density requires that these deep dielectric etches do not induce excessive stress or plasma charging damage, which could degrade the extremely thin underlying gate dielectrics or inadvertently shift device threshold voltages [T2]. Therefore, the multi-step PMD etch approach is employed to dynamically adjust the etch-to-passivation balance, preventing complete etch stop or severe profile distortion that would otherwise compromise the final metallization fill integrity [P3].