40nm BSI CMOS Image SensorPreview

CMOS Image Sensors, reaching the contact pads requires etching through a thick, composite PMD stack to form high-aspect-ratio contacts (HARC) [P1]. This step completes the deep contact profile before transitioning to the subsequent Inter-Layer Dielectric (ILD) processing steps, such as ILD 1-1 Etch [A2]. The ultimate goal is to provide a low-resistance path to the underlying device terminals, as minimizing parasitic contact resistance is a fundamental requirement for maintaining device drive capability and signal integrity [T1]. The PMD 5 Etch fundamentally utilizes reactive ion etching (RIE) to achieve a highly anisotropic structural profile [P1]. The process relies on the synergistic action of directional ion bombardment and neutral chemical radicals generated within a low-pressure discharge plasma [P1]. During the etch, polymerizing fluorocarbon species deposit a thin passivation layer on the feature sidewalls to prevent lateral etching [P3]. Concurrently, charged ions gain directional kinetic energy from the applied electric field to continuously clear the bottom passivation layer and drive the vertical etch rate [P1]. This delicate balance between chemical etching and physical sputtering must be tightly controlled via gas composition and RF bias to suppress detrimental phenomena such as RIE lag and bottom notching [P1]. Anisotropic dry etching is selected over wet etching because conventional isotropic chemical etching cannot meet the stringent critical dimension (CD) control required at advanced nanometer scales [P1]. To withstand the prolonged etch times required for deep PMD stacks, an amorphous carbon layer (ACL) hardmask is frequently employed to provide high etch selectivity [P3]. However, the subsequent removal of this ACL hardmask utilizing O2/Ar plasma must be carefully engineered; active oxygen radicals and VUV radiation can preferentially break weak bonds in surrounding dielectric materials, leading to surface decarbonization and unintended structural densification [P3]. Furthermore, integrating distinct dielectric etch-stop layers at the bottom of the PMD stack ensures that the etch terminates precisely, defining the contact location without destructive over-etching into the underlying conductive lines [A2]. At the 40nm node, the geometrical aspect ratio of these contact structures increases significantly, which severely restricts the transport of reactive neutral species and the extraction of volatile byproducts from the trench bottom (Engineering Practice). Minor deviations in the sidewall profile or incomplete etching can leave residual dielectric material, leading to substantially higher contact resistance or catastrophic open circuits [A1]. Therefore, advanced process control (APC) systems are essential to dynamically manage plasma parameters, thereby maintaining high dimensional fidelity and minimizing plasma-induced charge-up damage to the underlying active structures [P1].