As device dimensions shrink, plasma-induced phenomena such as the notch effect or RIE lag become significantly more pronounced, requiring advanced process control to maintain uniform etch depths across varying pattern densities .
In depth
In a Backside Illuminated (BSI) CMOS Image Sensor, the active photo
diode array receives light from the wafer backside, necessitating the exposure of frontside-routed bond pads through the thinned silicon substrate (Engineering Practice). Following the preliminary backside planarization and photolithography steps, the Si Etch step is executed to selectively remove the bulk silicon overlying the terminal metal pads . This process creates a deep via or trench structure that physically breaches the substrate, terminating precisely on the underlying pad oxide or Contact Etch Stop Layer (CESL) . As demonstrated in , anisotropic reactive-ion etching (RIE) applied from the wafer backside is essential for forming vertical interconnect pathways without degrading the surrounding integrated device architecture. By effectively clearing the silicon, this step directly prepares the structure for the subsequent Pad Oxide and CESL etch sequences, ensuring an unhindered electrical path to the bond pad . The silicon removal is driven by the synergistic chemical reaction and physical sputtering mechanism characteristic of plasma etching . Neutral radicals generated in the low-pressure discharge plasma dominate the chemical etching of the silicon lattice by reacting to form volatile byproducts . Concurrently, the applied radio-frequency (RF) field produces a self-bias on the electrode, accelerating positively charged ions toward the wafer surface . These energetic ions bombard the exposed silicon, enhancing the local chemical reaction rate at the trench bottom while suppressing lateral etching along the sidewalls, thereby yielding a highly anisotropic vertical profile . Furthermore, the addition of specific passivating gases modulates the plasma chemistry to form non-volatile polymeric films on the sidewalls, which prevents isotropic undercut and maintains critical dimensions . RIE is selected over traditional wet chemical etching because wet methods, such as KOH etching, are strongly restricted by crystal orientation and cannot achieve the vertical profiles required for dense advanced layouts . To prevent punch-through into the underlying dielectric layers, the plasma chemistry must be tuned to maximize the selectivity of silicon over silicon dioxide . This selectivity is often achieved by adjusting the ratio of etchant to passivant gases, where polymer-depositing precursors selectively protect the oxide while allowing continuous silicon consumption . Process parameters such as RF power, chamber pressure, and bias voltage interact dynamically to balance the physical ion bombardment flux with the chemical radical concentration . Excessive ion energy can lead to near-surface lattice displacement and amorphization, while insufficient energy risks severe RIE lag or incomplete clearing at the trench bottom . At the 40nm technology node, spatial scaling tightly constrains the allowable pitch and critical dimension (CD) of the backside pad openings (Engineering Practice). As device dimensions shrink, plasma-induced phenomena such as the notch effect or RIE lag become significantly more pronounced, requiring advanced process control to maintain uniform etch depths across varying pattern densities . Moreover, the proximity of the deep backside etch to the active transistors demands precise control of plasma-induced charging damage . Such charge accumulation can induce high electric fields that compromise gate oxide integrity, ultimately increasing the exponential subthreshold leakage current of adjacent circuitry . Therefore, balancing the anisotropic etch rate with stringent defectivity and profile control is a paramount engineering requirement for 40nm BSI packaging .
Risks & Challenges
[High] RIE Lag and Micro-loading: Etch depth variations occur because plasma species transport is restricted in narrow, high-aspect-ratio openings, causing smaller features to etch slower than larger ones . This leads to incomplete silicon removal over critical bond pads, blocking subsequent electrical contact (Engineering Practice).
[High] Plasma-Induced Surface Damage: High-energy positive ions accelerated by the self-bias voltage bombard the trench bottom, causing near-surface lattice displacement and severe amorphization . If the over-etch penetrates the protective pad oxide, this structural disorder can extend into the underlying conductive layers, drastically increasing contact resistance .
[Medium] Isotropic Undercut (Notching): Imbalanced plasma chemistry or insufficient sidewall passivation allows neutral radicals to spontaneously react with silicon along the lateral directions . This compromises the verticality of the via, potentially exposing adjacent isolated structures or causing mechanical instability in the bond pad opening .
[Medium] Plasma Charging Damage: During the plasma process, localized charge accumulation can occur at the bottom of the high-aspect-ratio trench due to differential electron and ion shading effects . This accumulated charge can induce high perpendicular electric fields across the underlying structures, leading to dielectric degradation and severe threshold voltage shifts in nearby field-effect transistors .
[Low] Polymer Residue Contamination: The use of passivating gases to enhance anisotropy promotes the deposition of non-volatile carbon- and fluorine-containing films on the silicon surface . If these insulating residues are not completely removed during the subsequent ashing step, they act as a barrier that prevents proper electrical connection to the bond pad (Engineering Practice).