Reactive Ion Etching is selected over wet anisotropic etching because it provides the strict dimensional control and vertical sidewalls required for high-density bond pad arrays .
In depth
In nanoscale Backside Illuminated (BSI) CMOS Image Sensors, accessing the front-side metal routing from the thinned b
ackside is essential for forming external electrical connections (Engineering Practice). Following the sequential etching of the Backside Passivation Metal Dielectric (BPMD) and Anti-Reflective/High-k Dielectric layers (HKD/AR2, HKD/AR1), the bulk silicon substrate is locally exposed . This specific "RIE etch, Si Back etch" step within the BONDPAD module is tasked with anisotropically removing the remaining silicon to form a deep trench or via that targets the front-side bond pads . Unlike earlier silicon back etches in the flow (such as pixel isolation or Poly/Si back etches) which define optical boundaries and active device isolation, this step is strictly optimized for deep, high-aspect-ratio vertical interconnect formation . It critically prepares the cavity for subsequent ashing, cleaning, and final pad opening steps that will eventually expose the underlying metal contact (Engineering Practice). The etch heavily relies on Deep Reactive Ion Etching (DRIE), frequently utilizing a time-multiplexed alternating process to achieve the required depth . The physical mechanism involves rapidly switching between isotropic silicon etching—typically using a fluorine-based plasma like SF6 —and sidewall passivation utilizing a deposited fluorocarbon polymer . Directional ion bombardment during the active etch phase selectively clears the polymer from the bottom horizontal surfaces while leaving the vertical sidewalls protected, enabling highly anisotropic profile evolution . However, this cyclical nature inevitably produces sidewall scallops, which are periodic geometric undulations along the via profile . Because the etch cavity extends toward the front-side active structures, the etch must be precisely controlled to prevent etchants from penetrating and chemically damaging the critical front-side components . Reactive Ion Etching is selected over wet anisotropic etching because it provides the strict dimensional control and vertical sidewalls required for high-density bond pad arrays . To mitigate the thermo-mechanical stress concentrations caused by severe sidewall scallops, process parameters such as gas flow ratios, plasma bias power, and cycle times are continuously tuned to minimize scallop depth . Furthermore, excessive sharp angles at the trench bottom can cause electric field crowding and generate localized surface states that dramatically increase dark current or white pixel defects in the adjacent image sensor array . Therefore, the final stages of this Si back etch often incorporate smoothing or chamfering steps to modify the trench cross-section and reduce stress . In-line metrology, such as spectroscopic reflectometry, is commonly utilized to non-destructively monitor the depth and sidewall angle of these etched structures by analyzing optical interference patterns within the cavities . In 40nm BSI technology, the ultra-thin nature of the bonded silicon substrate leaves a significantly narrowed process window for over-etching . Consequently, the etch process must exhibit extremely high chemical selectivity to the underlying front-side inter-layer dielectric (ILD) or specifically designed etch-stop layers to prevent catastrophic punch-through . Precise control of the via dimensions is necessary to ensure the uniform subsequent deposition of isolation and barrier layers . Failure to maintain this precise profile can lead to non-conformal step coverage, creating leakage pathways that fundamentally compromise the strict low-noise requirements of the advanced image sensor (Engineering Practice).
Risks & Challenges
[High] Etch Punch-Through / Front-Side Damage: If the etch rate is locally accelerated or the silicon thickness is non-uniform, the etchant can penetrate the intended etch-stop structure and attack the front-side active devices or interconnects . This failure mode leads to immediate structural damage and catastrophic yield loss (Engineering Practice).
[Medium] Thermo-Mechanical Stress-Induced Cracking: The cyclical Bosch process inherently generates sidewall scallops that act as sharp geometric stress concentrators . During subsequent thermal cycling, the coefficient of thermal expansion (CTE) mismatch between the silicon substrate and later-deposited barrier or metal fill materials can cause localized high stresses, leading to dielectric cracking and electrical leakage .
[Medium] Dark Current / White Pixel Generation: Sharp structural corners formed at the bottom of the etched trench can cause severe electric field concentration and generate interface trap states . This enhances surface carrier generation and recombination, which diffuses into the adjacent photodiode array and manifests as elevated dark current and white pixel defects .
[Low] Incomplete Silicon Removal (Under-Etch): Due to reactive ion micro-loading effects or insufficient reactive species transport in high-aspect-ratio structures, the etch may fail to reach the target landing pad . This leaves residual silicon at the trench bottom, which impedes the formation of a low-resistance ohmic contact during subsequent metallization steps .